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https://github.com/espressif/esp-idf.git
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be53a6950c
SPI flash hardware sends 52h command, which is a 32KB erase. There is a matching bug in the ROM SPIEraseArea code, unless flashchip->block_size is modified first.
528 lines
18 KiB
C
528 lines
18 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ROM_SPI_FLASH_H_
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#define _ROM_SPI_FLASH_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/spi_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup spi_flash_apis, spi flash operation related apis
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* @brief spi_flash apis
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*/
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/** @addtogroup spi_flash_apis
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* @{
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*/
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/*************************************************************
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* Note
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*************************************************************
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* 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
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* used as an SPI master to access Flash and ext-SRAM by
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* Cache module. It will support Decryto read for Flash,
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* read/write for ext-SRAM. And SPI1 is also used as an
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* SPI master for Flash read/write and ext-SRAM read/write.
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* It will support Encrypto write for Flash.
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* 2. As an SPI master, SPI support Highest clock to 80M,
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* however, Flash with 80M Clock should be configured
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* for different Flash chips. If you want to use 80M
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* clock We should use the SPI that is certified by
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* Espressif. However, the certification is not started
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* at the time, so please use 40M clock at the moment.
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* 3. SPI Flash can use 2 lines or 4 lines mode. If you
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* use 2 lines mode, you can save two pad SPIHD and
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* SPIWP for gpio. ESP32 support configured SPI pad for
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* Flash, the configuration is stored in efuse and flash.
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* However, the configurations of pads should be certified
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* by Espressif. If you use this function, please use 40M
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* clock at the moment.
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* 4. ESP32 support to use Common SPI command to configure
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* Flash to QIO mode, if you failed to configure with fix
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* command. With Common SPI Command, ESP32 can also provide
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* a way to use same Common SPI command groups on different
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* Flash chips.
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* 5. This functions are not protected by packeting, Please use the
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*************************************************************
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*/
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#define PERIPHS_SPI_FLASH_CMD SPI_CMD(1)
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#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR(1)
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#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(1)
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#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1(1)
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#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS(1)
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#define PERIPHS_SPI_FLASH_USRREG SPI_USER(1)
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#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1(1)
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#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2(1)
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#define PERIPHS_SPI_FLASH_C0 SPI_W0(1)
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#define PERIPHS_SPI_FLASH_C1 SPI_W1(1)
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#define PERIPHS_SPI_FLASH_C2 SPI_W2(1)
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#define PERIPHS_SPI_FLASH_C3 SPI_W3(1)
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#define PERIPHS_SPI_FLASH_C4 SPI_W4(1)
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#define PERIPHS_SPI_FLASH_C5 SPI_W5(1)
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#define PERIPHS_SPI_FLASH_C6 SPI_W6(1)
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#define PERIPHS_SPI_FLASH_C7 SPI_W7(1)
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#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC(1)
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#define SPI0_R_QIO_DUMMY_CYCLELEN 3
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#define SPI0_R_QIO_ADDR_BITSLEN 31
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#define SPI0_R_FAST_DUMMY_CYCLELEN 7
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#define SPI0_R_DIO_DUMMY_CYCLELEN 3
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#define SPI0_R_FAST_ADDR_BITSLEN 23
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#define SPI0_R_SIO_ADDR_BITSLEN 23
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#define SPI1_R_QIO_DUMMY_CYCLELEN 3
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#define SPI1_R_QIO_ADDR_BITSLEN 31
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#define SPI1_R_FAST_DUMMY_CYCLELEN 7
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#define SPI1_R_DIO_DUMMY_CYCLELEN 3
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#define SPI1_R_DIO_ADDR_BITSLEN 31
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#define SPI1_R_FAST_ADDR_BITSLEN 23
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#define SPI1_R_SIO_ADDR_BITSLEN 23
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#define SPI_W_SIO_ADDR_BITSLEN 23
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#define TWO_BYTE_STATUS_EN SPI_WRSR_2B
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//SPI address register
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#define SPI_FLASH_BYTES_LEN 24
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#define SPI_BUFF_BYTE_WRITE_NUM 32
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#define SPI_BUFF_BYTE_READ_NUM 64
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#define SPI_BUFF_BYTE_READ_BITS 0x3f
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//SPI status register
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#define SPI_FLASH_BUSY_FLAG BIT0
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#define SPI_FLASH_WRENABLE_FLAG BIT1
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#define SPI_FLASH_BP0 BIT2
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#define SPI_FLASH_BP1 BIT3
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#define SPI_FLASH_BP2 BIT4
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#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2)
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#define SPI_FLASH_QE BIT9
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typedef enum {
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SPI_FLASH_QIO_MODE = 0,
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SPI_FLASH_QOUT_MODE,
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SPI_FLASH_DIO_MODE,
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SPI_FLASH_DOUT_MODE,
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SPI_FLASH_FASTRD_MODE,
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SPI_FLASH_SLOWRD_MODE
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} SpiFlashRdMode;
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typedef enum {
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SPI_FLASH_RESULT_OK,
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SPI_FLASH_RESULT_ERR,
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SPI_FLASH_RESULT_TIMEOUT
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} SpiFlashOpResult;
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typedef struct {
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uint32_t deviceId;
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uint32_t chip_size; // chip size in bytes
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uint32_t block_size;
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uint32_t sector_size;
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uint32_t page_size;
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uint32_t status_mask;
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} SpiFlashChip;
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typedef struct {
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uint8_t data_length;
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uint8_t read_cmd0;
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uint8_t read_cmd1;
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uint8_t write_cmd;
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uint16_t data_mask;
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uint16_t data;
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} SpiCommonCmd;
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/**
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* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
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* Please do not call this function in SDK.
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*
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* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
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*
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* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
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*
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* @return None
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*/
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void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
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/**
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* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
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* Please do not call this function in SDK.
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*
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* @param uint8_t wp_gpio_num: WP gpio number.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @return None
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*/
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void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi);
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/**
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* @brief Set SPI Flash pad drivers.
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* Please do not call this function in SDK.
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*
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* @param uint8_t wp_gpio_num: WP gpio number.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
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* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
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* Values usually read from falsh by rom code, function usually callde by rom code.
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* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
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*
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* @return None
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*/
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void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
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/**
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* @brief Select SPI Flash function for pads.
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* Please do not call this function in SDK.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @return None
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*/
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void SelectSpiFunction(uint32_t ishspi);
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/**
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* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
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* Please do not call this function in SDK.
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*
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* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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*
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* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
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*
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* @return None
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*/
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void spi_flash_attach(uint32_t ishspi, bool legacy);
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/**
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* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
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* Please do not call this function in SDK.
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*
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* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
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*
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* @param uint32_t *status : The pointer to which to return the Flash status value.
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*
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* @return SPI_FLASH_RESULT_OK : read OK.
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* SPI_FLASH_RESULT_ERR : read error.
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* SPI_FLASH_RESULT_TIMEOUT : read timeout.
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*/
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SpiFlashOpResult SPI_read_status(SpiFlashChip *spi, uint32_t *status);
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/**
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* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
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* Please do not call this function in SDK.
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*
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* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
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*
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* @param uint32_t *status : The pointer to which to return the Flash status value.
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*
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* @return SPI_FLASH_RESULT_OK : read OK.
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* SPI_FLASH_RESULT_ERR : read error.
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* SPI_FLASH_RESULT_TIMEOUT : read timeout.
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*/
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SpiFlashOpResult SPI_read_status_high(uint32_t *status);
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/**
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* @brief Write status to Falsh status register.
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* Please do not call this function in SDK.
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*
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* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
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*
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* @param uint32_t status_value : Value to .
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*
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* @return SPI_FLASH_RESULT_OK : write OK.
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* SPI_FLASH_RESULT_ERR : write error.
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* SPI_FLASH_RESULT_TIMEOUT : write timeout.
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*/
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SpiFlashOpResult SPI_write_status(SpiFlashChip *spi, uint32_t status_value);
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/**
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* @brief Use a command to Read Flash status register.
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* Please do not call this function in SDK.
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*
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* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
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*
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* @param uint32_t*status : The pointer to which to return the Flash status value.
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*
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* @return SPI_FLASH_RESULT_OK : read OK.
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* SPI_FLASH_RESULT_ERR : read error.
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* SPI_FLASH_RESULT_TIMEOUT : read timeout.
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*/
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SpiFlashOpResult SPI_user_command_read(uint32_t *status, uint8_t cmd);
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/**
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* @brief Config SPI Flash read mode when init.
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* Please do not call this function in SDK.
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*
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* @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
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*
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* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
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*
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* @return SPI_FLASH_RESULT_OK : config OK.
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* SPI_FLASH_RESULT_ERR : config error.
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* SPI_FLASH_RESULT_TIMEOUT : config timeout.
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*/
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SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy);
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/**
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* @brief Config SPI Flash read mode when Flash is running in some mode.
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* Please do not call this function in SDK.
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*
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* @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
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*
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* @return SPI_FLASH_RESULT_OK : config OK.
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* SPI_FLASH_RESULT_ERR : config error.
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* SPI_FLASH_RESULT_TIMEOUT : config timeout.
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*/
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SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode);
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/**
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* @brief Config SPI Flash clock divisor.
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* Please do not call this function in SDK.
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*
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* @param uint8_t freqdiv: clock divisor.
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*
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* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
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*
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* @return SPI_FLASH_RESULT_OK : config OK.
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* SPI_FLASH_RESULT_ERR : config error.
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* SPI_FLASH_RESULT_TIMEOUT : config timeout.
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*/
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SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi);
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/**
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* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
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* Please do not call this function in SDK.
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*
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* @param SpiCommonCmd *cmd : A struct to show the action of a command.
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*
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* @return uint16_t 0 : do not send command any more.
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* 1 : go to the next command.
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* n > 1 : skip (n - 1) commands.
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*/
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uint16_t SPI_Common_Command(SpiCommonCmd *cmd);
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/**
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* @brief Unlock SPI write protect.
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* Please do not call this function in SDK.
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*
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* @param None.
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*
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* @return SPI_FLASH_RESULT_OK : Unlock OK.
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* SPI_FLASH_RESULT_ERR : Unlock error.
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* SPI_FLASH_RESULT_TIMEOUT : Unlock timeout.
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*/
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SpiFlashOpResult SPIUnlock(void);
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/**
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* @brief SPI write protect.
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* Please do not call this function in SDK.
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*
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* @param None.
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*
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* @return SPI_FLASH_RESULT_OK : Lock OK.
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* SPI_FLASH_RESULT_ERR : Lock error.
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* SPI_FLASH_RESULT_TIMEOUT : Lock timeout.
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*/
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SpiFlashOpResult SPILock(void);
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/**
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* @brief Update SPI Flash parameter.
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* Please do not call this function in SDK.
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*
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* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
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*
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* @param uint32_t chip_size : The Flash size.
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*
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* @param uint32_t block_size : The Flash block size.
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*
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* @param uint32_t sector_size : The Flash sector size.
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*
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* @param uint32_t page_size : The Flash page size.
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*
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* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
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*
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* @return SPI_FLASH_RESULT_OK : Update OK.
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* SPI_FLASH_RESULT_ERR : Update error.
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* SPI_FLASH_RESULT_TIMEOUT : Update timeout.
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*/
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SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
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/**
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* @brief Erase whole flash chip.
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* Please do not call this function in SDK.
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*
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* @param None
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*
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* @return SPI_FLASH_RESULT_OK : Erase OK.
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* SPI_FLASH_RESULT_ERR : Erase error.
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* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
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*/
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SpiFlashOpResult SPIEraseChip(void);
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/**
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* @brief Erase a 32KB block of flash
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* Uses SPI flash command 52h.
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* Please do not call this function in SDK.
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*
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* @param uint32_t block_num : Which block to erase.
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*
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* @return SPI_FLASH_RESULT_OK : Erase OK.
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* SPI_FLASH_RESULT_ERR : Erase error.
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* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
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*/
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SpiFlashOpResult SPIEraseBlock(uint32_t block_num);
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/**
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* @brief Erase a sector of flash.
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* Please do not call this function in SDK.
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*
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* @param uint32_t sector_num : Which sector to erase.
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*
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* @return SPI_FLASH_RESULT_OK : Erase OK.
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* SPI_FLASH_RESULT_ERR : Erase error.
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* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
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*/
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SpiFlashOpResult SPIEraseSector(uint32_t sector_num);
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/**
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* @brief Erase some sectors.
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* Please do not call this function in SDK.
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*
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* @note If calling this function, first set
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* g_rom_flashchip.block_size = 32768; or call SPIParamCfg()
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* with appropriate parameters. This is due to a ROM bug, the
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* block erase command in use is a 32KB erase but after reset
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* the block_size field is incorrectly set to 65536.
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*
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* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
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*
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* @param uint32_t area_len : Length to erase, should be sector aligned.
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*
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* @return SPI_FLASH_RESULT_OK : Erase OK.
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* SPI_FLASH_RESULT_ERR : Erase error.
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* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
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*/
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SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len);
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/**
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* @brief Write Data to Flash, you should Erase it yourself if need.
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* Please do not call this function in SDK.
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*
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* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
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*
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* @param const uint32_t *src : The pointer to data which is to write.
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*
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* @param uint32_t len : Length to write, should be 4 bytes aligned.
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*
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* @return SPI_FLASH_RESULT_OK : Write OK.
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* SPI_FLASH_RESULT_ERR : Write error.
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* SPI_FLASH_RESULT_TIMEOUT : Write timeout.
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*/
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SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len);
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/**
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* @brief Read Data from Flash, you should Erase it yourself if need.
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* Please do not call this function in SDK.
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*
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* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
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*
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* @param uint32_t *dest : The buf to read the data.
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*
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* @param uint32_t len : Length to read, should be 4 bytes aligned.
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*
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* @return SPI_FLASH_RESULT_OK : Read OK.
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* SPI_FLASH_RESULT_ERR : Read error.
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* SPI_FLASH_RESULT_TIMEOUT : Read timeout.
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*/
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SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len);
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/**
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* @brief SPI1 go into encrypto mode.
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* Please do not call this function in SDK.
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*
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* @param None
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*
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* @return None
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*/
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void SPI_Write_Encrypt_Enable(void);
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/**
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* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
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* Please do not call this function in SDK.
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*
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* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
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*
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* @param uint32_t *data : The pointer to data which is to write.
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*
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* @return SPI_FLASH_RESULT_OK : Prepare OK.
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* SPI_FLASH_RESULT_ERR : Prepare error.
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* SPI_FLASH_RESULT_TIMEOUT : Prepare timeout.
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*/
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SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data);
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/**
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* @brief SPI1 go out of encrypto mode.
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* Please do not call this function in SDK.
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*
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* @param None
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*
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* @return None
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*/
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void SPI_Write_Encrypt_Disable(void);
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/**
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* @brief Encrpto writing data to flash, you should Erase it yourself if need.
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* Please do not call this function in SDK.
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*
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* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
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*
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* @param uint32_t *data : The pointer to data which is to write.
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*
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* @param uint32_t len : Length to write, should be 32 bytes aligned.
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*
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* @return SPI_FLASH_RESULT_OK : Encrypto write OK.
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* SPI_FLASH_RESULT_ERR : Encrypto write error.
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* SPI_FLASH_RESULT_TIMEOUT : Encrypto write timeout.
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*/
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SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t len);
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/** @brief Global SpiFlashChip structure used by ROM functions
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*
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*/
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extern SpiFlashChip g_rom_flashchip;
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_SPI_FLASH_H_ */
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