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https://github.com/espressif/esp-idf.git
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24484887a9
If the TimerGroup 0 clock is disabled and then reenabled, the watchdog registers (Flashboot protection included) will be re-enabled, and some seconds later, will trigger an unintended reset. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
318 lines
13 KiB
C
318 lines
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/rtc.h"
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#include "soc/dport_reg.h"
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#include "soc/i2s_reg.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_clk.h"
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#include "bootloader_clock.h"
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#include "hal/wdt_hal.h"
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#include "esp_private/spi_common_internal.h" // [refactor-todo]: for spicommon_periph_in_use
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#include "esp_log.h"
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#include "esp_cpu.h"
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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#include "sdkconfig.h"
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static const char* TAG = "clk";
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/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
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* Larger values increase startup delay. Smaller values may cause false positive
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* detection (i.e. oscillator runs for a few cycles and then stops).
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*/
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#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
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#ifdef CONFIG_RTC_XTAL_CAL_RETRY
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#define RTC_XTAL_CAL_RETRY CONFIG_RTC_XTAL_CAL_RETRY
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#else
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#define RTC_XTAL_CAL_RETRY 1
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#endif
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/* Indicates that this 32k oscillator gets input from external oscillator, rather
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* than a crystal.
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*/
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#define EXT_OSC_FLAG BIT(3)
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/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define
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* an extra enum member for the external 32k oscillator.
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* For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values.
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*/
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typedef enum {
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SLOW_CLK_150K = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator
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SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL
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SLOW_CLK_8MD256 = SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, //!< Internal 8 MHz RC oscillator, divided by 256
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SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
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} slow_clk_sel_t;
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static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
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{
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soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
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uint32_t cal_val = 0;
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/* number of times to repeat 32k XTAL calibration
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* before giving up and switching to the internal RC
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*/
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int retry_32k_xtal = RTC_XTAL_CAL_RETRY;
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do {
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if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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/* 32k XTAL oscillator needs to be enabled and running before it can
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* be used. Hardware doesn't have a direct way of checking if the
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* oscillator is running. Here we use rtc_clk_cal function to count
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* the number of main XTAL cycles in the given number of 32k XTAL
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* oscillator cycles. If the 32k XTAL has not started up, calibration
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* will time out, returning 0.
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*/
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ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
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if (slow_clk == SLOW_CLK_32K_XTAL) {
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rtc_clk_32k_enable(true);
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} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
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rtc_clk_32k_enable_external();
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}
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// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
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if (SLOW_CLK_CAL_CYCLES > 0) {
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cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
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if (cal_val == 0) {
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if (retry_32k_xtal-- > 0) {
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continue;
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}
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ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
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rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
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}
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}
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} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
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rtc_clk_8m_enable(true, true);
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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*/
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cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
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} else {
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
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}
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} while (cal_val == 0);
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
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esp_clk_slowclk_cal_set(cal_val);
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}
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__attribute__((weak)) void esp_clk_init(void)
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{
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rtc_config_t cfg = RTC_CONFIG_DEFAULT();
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rtc_init(cfg);
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#if (CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS || CONFIG_APP_INIT_CLK)
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/* Check the bootloader set the XTAL frequency.
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Bootloaders pre-v2.1 don't do this.
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*/
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
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ESP_EARLY_LOGW(TAG, "RTC domain not initialised by bootloader");
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bootloader_clock_configure();
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}
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#else
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/* If this assertion fails, either upgrade the bootloader or enable CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
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assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
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#endif
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bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
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rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
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rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
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// If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
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// Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
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// This prevents excessive delay before resetting in case the supply voltage is drawdown.
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// (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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//Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
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#elif defined(CONFIG_RTC_CLK_SRC_INT_8MD256)
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select_rtc_slow_clk(SLOW_CLK_8MD256);
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#else
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select_rtc_slow_clk(SLOW_CLK_150K);
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// After changing a frequency WDT timeout needs to be set for new frequency.
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stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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rtc_cpu_freq_config_t old_config;
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rtc_cpu_freq_config_t new_config;
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rtc_clk_cpu_freq_get_config(&old_config);
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const uint32_t old_freq_mhz = old_config.freq_mhz;
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const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
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bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
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assert(res);
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// Wait for UART TX to finish, otherwise some UART output will be lost
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// when switching APB frequency
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if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
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esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
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}
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if (res) {
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rtc_clk_cpu_freq_set_config(&new_config);
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}
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// Re calculate the ccount to make time calculation correct.
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esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
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}
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/* This function is not exposed as an API at this point.
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* All peripheral clocks are default enabled after chip is powered on.
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* This function disables some peripheral clocks when cpu starts.
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* These peripheral clocks are enabled when the peripherals are initialized
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* and disabled when they are de-initialized.
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*/
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__attribute__((weak)) void esp_perip_clk_init(void)
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{
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uint32_t common_perip_clk;
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uint32_t hwcrypto_perip_clk;
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uint32_t wifi_bt_sdio_clk;
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#if CONFIG_FREERTOS_UNICORE
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soc_reset_reason_t rst_reas[1];
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#else
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soc_reset_reason_t rst_reas[2];
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#endif
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rst_reas[0] = esp_rom_get_reset_reason(0);
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#if !CONFIG_FREERTOS_UNICORE
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rst_reas[1] = esp_rom_get_reset_reason(1);
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#endif
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/* For reason that only reset CPU, do not disable the clocks
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* that have been enabled before reset.
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*/
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if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT)
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#if !CONFIG_FREERTOS_UNICORE
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|| (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT)
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#endif
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) {
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common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
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hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
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wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
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}
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else {
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common_perip_clk = DPORT_WDG_CLK_EN |
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DPORT_PCNT_CLK_EN |
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DPORT_LEDC_CLK_EN |
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DPORT_TIMERGROUP1_CLK_EN |
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DPORT_PWM0_CLK_EN |
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DPORT_TWAI_CLK_EN |
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DPORT_PWM1_CLK_EN |
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DPORT_PWM2_CLK_EN |
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DPORT_PWM3_CLK_EN;
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hwcrypto_perip_clk = DPORT_PERI_EN_AES |
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DPORT_PERI_EN_SHA |
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DPORT_PERI_EN_RSA |
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DPORT_PERI_EN_SECUREBOOT;
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wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
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DPORT_WIFI_CLK_BT_EN_M |
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DPORT_WIFI_CLK_UNUSED_BIT5 |
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DPORT_WIFI_CLK_UNUSED_BIT12 |
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DPORT_WIFI_CLK_SDIOSLAVE_EN |
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DPORT_WIFI_CLK_SDIO_HOST_EN |
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DPORT_WIFI_CLK_EMAC_EN;
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}
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//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
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common_perip_clk |= DPORT_I2S0_CLK_EN |
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#if CONFIG_ESP_CONSOLE_UART_NUM != 0
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DPORT_UART_CLK_EN |
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#endif
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#if CONFIG_ESP_CONSOLE_UART_NUM != 1
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DPORT_UART1_CLK_EN |
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#endif
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#if CONFIG_ESP_CONSOLE_UART_NUM != 2
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DPORT_UART2_CLK_EN |
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#endif
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DPORT_SPI2_CLK_EN |
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DPORT_I2C_EXT0_CLK_EN |
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DPORT_UHCI0_CLK_EN |
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DPORT_RMT_CLK_EN |
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DPORT_UHCI1_CLK_EN |
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DPORT_SPI3_CLK_EN |
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DPORT_I2C_EXT1_CLK_EN |
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DPORT_I2S1_CLK_EN |
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DPORT_SPI_DMA_CLK_EN;
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common_perip_clk &= ~DPORT_SPI01_CLK_EN;
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#if CONFIG_SPIRAM_SPEED_80M
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//80MHz SPIRAM uses SPI2/SPI3 as well; it's initialized before this is called. Because it is used in
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//a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
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//in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
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//not modify that state, regardless of what we calculated earlier.
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if (spicommon_periph_in_use(HSPI_HOST)) {
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common_perip_clk &= ~DPORT_SPI2_CLK_EN;
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}
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if (spicommon_periph_in_use(VSPI_HOST)) {
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common_perip_clk &= ~DPORT_SPI3_CLK_EN;
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}
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#endif
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/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
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* the current is not reduced when disable I2S clock.
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*/
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DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(0), I2S_CLKA_ENA);
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DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(1), I2S_CLKA_ENA);
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/* Disable some peripheral clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
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/* Disable hardware crypto clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
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DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
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/* Disable WiFi/BT/SDIO clocks. */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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/* Enable TimerGroup 0 clock to ensure its reference counter will never
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* be decremented to 0 during normal operation and preventing it from
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* being disabled.
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* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
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* registers (Flashboot protection included) will be reenabled, and some
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* seconds later, will trigger an unintended reset.
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*/
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periph_module_enable(PERIPH_TIMG0_MODULE);
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}
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void rtc_clk_select_rtc_slow_clk(void)
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{
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select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
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}
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