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73 lines
1.1 KiB
Plaintext
73 lines
1.1 KiB
Plaintext
#####################################################
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# This file is auto-generated from SoC caps
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# using gen_soc_caps_kconfig.py, do not edit manually
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#####################################################
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config ESP_ROM_HAS_CRC_LE
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bool
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default y
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config ESP_ROM_HAS_CRC_BE
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bool
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default y
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config ESP_ROM_UART_CLK_IS_XTAL
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bool
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default y
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config ESP_ROM_USB_SERIAL_DEVICE_NUM
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int
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default 6
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config ESP_ROM_USB_OTG_NUM
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int
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default 5
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config ESP_ROM_HAS_RETARGETABLE_LOCKING
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bool
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default y
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config ESP_ROM_GET_CLK_FREQ
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bool
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default y
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config ESP_ROM_HAS_RVFPLIB
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bool
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default y
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config ESP_ROM_HAS_HAL_WDT
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bool
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default y
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config ESP_ROM_HAS_HAL_SYSTIMER
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bool
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default y
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config ESP_ROM_HAS_LAYOUT_TABLE
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bool
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default y
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config ESP_ROM_WDT_INIT_PATCH
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bool
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default y
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config ESP_ROM_HAS_LP_ROM
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bool
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default y
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config ESP_ROM_WITHOUT_REGI2C
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bool
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default y
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config ESP_ROM_HAS_NEWLIB
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bool
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default y
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config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
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bool
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default y
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config ESP_ROM_HAS_VERSION
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bool
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default y
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