mirror of
https://github.com/espressif/esp-idf.git
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2d44dc1eed
This commit gives basic mmu driver framework. Now it is able to maintain mmu virtual address usage on esp32, esp32s2 and esp32s3. Usage to external virtual address should rely on mmu functions to know which address range is available, instead of hardcoded. This commit also improves psram memory that is added to the heap allocator. Now it's added to the heap, according to the memory alignment. Closes https://github.com/espressif/esp-idf/issues/8295
150 lines
5.3 KiB
C
150 lines
5.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*IRAM0 is connected with Cache IBUS0*/
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#define IRAM0_ADDRESS_LOW 0x40000000
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#define IRAM0_ADDRESS_HIGH 0x44000000
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#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
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#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
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/*DRAM0 is connected with Cache DBUS0*/
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#define DRAM0_ADDRESS_LOW 0x3C000000
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#define DRAM0_ADDRESS_HIGH 0x40000000
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#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
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#define DRAM0_CACHE_ADDRESS_HIGH 0x3E000000
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#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
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#define ESP_CACHE_TEMP_ADDR 0x3C800000
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#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
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#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
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#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
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#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
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#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
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#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
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#define CACHE_IBUS 0
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#define CACHE_IBUS_MMU_START 0
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#define CACHE_IBUS_MMU_END 0x800
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#define CACHE_DBUS 1
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#define CACHE_DBUS_MMU_START 0
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#define CACHE_DBUS_MMU_END 0x800
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//TODO, remove these cache function dependencies
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#define CACHE_IROM_MMU_START 0
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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#define CACHE_DROM_MMU_MAX_END 0x400
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#define ICACHE_MMU_SIZE 0x800
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#define DCACHE_MMU_SIZE 0x800
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#define MMU_BUS_START(i) 0
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#define MMU_BUS_SIZE(i) 0x800
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#define MMU_INVALID BIT(14)
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#define MMU_VALID 0
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#define MMU_TYPE BIT(15)
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#define MMU_ACCESS_FLASH 0
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#define MMU_ACCESS_SPIRAM BIT(15)
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#define CACHE_MAX_SYNC_NUM 0x400000
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#define CACHE_MAX_LOCK_NUM 0x8000
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#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
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#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
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/**
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* MMU entry valid bit mask for mapping value. For an entry:
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* valid bit + value bits
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* valid bit is BIT(14), so value bits are 0x3fff
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*/
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#define MMU_VALID_VAL_MASK 0x3fff
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/**
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* Max MMU available paddr page num.
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* `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
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* 16384 * 64KB, means MMU can support 1GB paddr at most
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*/
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#define MMU_MAX_PADDR_PAGE_NUM 16384
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/**
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* This is the mask used for mapping. e.g.:
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* 0x4200_0000 & MMU_VADDR_MASK
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*/
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#define MMU_VADDR_MASK 0x1FFFFFF
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//MMU entry num
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#define MMU_ENTRY_NUM 512
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#define CACHE_ICACHE_LOW_SHIFT 0
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#define CACHE_ICACHE_HIGH_SHIFT 2
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#define CACHE_DCACHE_LOW_SHIFT 4
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#define CACHE_DCACHE_HIGH_SHIFT 6
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#define CACHE_MEMORY_IBANK0_ADDR 0x40370000
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#define CACHE_MEMORY_IBANK1_ADDR 0x40374000
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#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000
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#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000
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#define SOC_MMU_DBUS_VADDR_BASE 0x3C000000
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#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
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/*------------------------------------------------------------------------------
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* MMU Linear Address
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*----------------------------------------------------------------------------*/
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/**
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* - 64KB MMU page size: the last 0xFFFF, which is the offset
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* - 512 MMU entries, needs 0x1FF to hold it.
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*
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* Therefore, 0x1FF,FFFF
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*/
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#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF
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/**
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* - If high linear address isn't 0, this means MMU can recognize these addresses
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* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
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* Under this condition, we use the max linear space.
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*/
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#else
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
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#endif
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#else
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
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#endif
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/**
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* I/D share the MMU linear address range
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*/
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_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
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#ifdef __cplusplus
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}
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#endif
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