LonerDan 0c741bc3ee fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V ... According to the ESP32-S2/S3 TRM, the output pin's mode is set in the RTC_GPIO_PINn_REG by programming the RTC_GPIO_PINn_PAD_DRIVER bit. The current ULP RISC-V RTCIO driver however, incorrectly programs the RTC_IO_TOUCH_PADn_REG register field RTC_IO_TOUCH_PADn_DRV. This commit fixes the bug.		2024-06-19 09:01:42 +02:00
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include	fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V	2024-06-19 09:01:42 +02:00
start.S	ulp-riscv: add support for using ADC as well as an example show-casing it.	2022-07-11 09:31:22 +08:00
ulp_riscv_adc.c	ulp: migrate tests to pytest embedded	2022-08-03 09:36:17 +08:00
ulp_riscv_i2c.c	ulp-riscv-i2c: Add ULP RISC-V I2C read/write timeout config option	2023-05-09 11:17:01 +02:00
ulp_riscv_lock.c	ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.	2022-08-05 18:16:31 +08:00
ulp_riscv_print.c	Add ULP-RISCV print and bitbanged UART tx API	2022-07-29 12:18:01 +08:00
ulp_riscv_touch.c	ulp-riscv-touch: Added support for the touch sensor on ULP RISC-V	2023-06-09 08:41:34 +02:00
ulp_riscv_uart.c	Add ULP-RISCV print and bitbanged UART tx API	2022-07-29 12:18:01 +08:00
ulp_riscv_utils.c	ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2	2022-12-27 07:44:26 +00:00