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110 lines
2.8 KiB
C
110 lines
2.8 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ESP_CPU_H
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#define _ESP_CPU_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "hal/cpu_hal.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ESP_WATCHPOINT_LOAD 0x40000000
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#define ESP_WATCHPOINT_STORE 0x80000000
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#define ESP_WATCHPOINT_ACCESS 0xC0000000
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typedef uint32_t esp_cpu_ccount_t;
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/** @brief Read current stack pointer address
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*
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*/
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static inline void *esp_cpu_get_sp(void)
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{
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return cpu_hal_get_sp();
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}
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/**
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* @brief Stall CPU using RTC controller
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* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
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*/
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void esp_cpu_stall(int cpu_id);
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/**
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* @brief Un-stall CPU using RTC controller
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* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
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*/
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void esp_cpu_unstall(int cpu_id);
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/**
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* @brief Reset CPU using RTC controller
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* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
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*/
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void esp_cpu_reset(int cpu_id);
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/**
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* @brief Returns true if a JTAG debugger is attached to CPU
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* OCD (on chip debug) port.
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*
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* @note If "Make exception and panic handlers JTAG/OCD aware"
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* is disabled, this function always returns false.
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*/
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bool esp_cpu_in_ocd_debug_mode(void);
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static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
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{
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return cpu_hal_get_cycle_count();
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}
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static inline void esp_cpu_set_ccount(esp_cpu_ccount_t val)
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{
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cpu_hal_set_cycle_count(val);
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}
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/**
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* @brief Set a watchpoint to break/panic when a certain memory range is accessed.
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*
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* @param no Watchpoint number. On the ESP32, this can be 0 or 1.
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* @param adr Base address to watch
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* @param size Size of the region, starting at the base address, to watch. Must
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* be one of 2^n, with n in [0..6].
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* @param flags One of ESP_WATCHPOINT_* flags
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*
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* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
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*
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* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
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* masking away the lower n bits for a region with size 2^n. If adr does
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* not have zero for these lower n bits, you may not be watching the
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* region you intended.
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*/
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esp_err_t esp_cpu_set_watchpoint(int no, void *adr, int size, int flags);
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/**
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* @brief Clear a watchpoint
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*
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* @param no Watchpoint to clear
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*
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*/
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void esp_cpu_clear_watchpoint(int no);
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#ifdef __cplusplus
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}
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#endif
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#endif // _ESP_CPU_H
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