mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
4dc2ace0b7
1) Added new Key Manager APIs
2) Added crypto locking layer for Key Manager
3) Remove support for deploying known key
4) Format key manager support
5) Fix build header error
6) Updated the key_mgr_types.h file
7) Added key manager tests
352 lines
14 KiB
C
352 lines
14 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** KEYMNG_CLK_REG register
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* Key Manager clock gate control register
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*/
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#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
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/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
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* Write 1 to force on register clock gate.
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*/
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#define KEYMNG_CLK_EN (BIT(0))
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#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
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#define KEYMNG_CLK_EN_V 0x00000001U
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#define KEYMNG_CLK_EN_S 0
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/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
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* Write 1 to force on memory clock gate.
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*/
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#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
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#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
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#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
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#define KEYMNG_MEM_CG_FORCE_ON_S 1
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/** KEYMNG_INT_RAW_REG register
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* Key Manager interrupt raw register, valid in level.
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*/
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#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
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/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
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#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
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#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_RAW_S 0
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/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
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#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
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#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_RAW_S 1
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/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
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#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
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#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_RAW_S 2
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/** KEYMNG_INT_ST_REG register
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* Key Manager interrupt status register.
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*/
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#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
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/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
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#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
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#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_ST_S 0
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/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
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#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
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#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_ST_S 1
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/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
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* The masked interrupt status bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_ST (BIT(2))
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#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
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#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_ST_S 2
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/** KEYMNG_INT_ENA_REG register
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* Key Manager interrupt enable register.
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*/
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#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
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/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
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#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
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#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_ENA_S 0
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/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
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#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
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#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_ENA_S 1
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/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
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* The interrupt enable bit for the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
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#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
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#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_ENA_S 2
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/** KEYMNG_INT_CLR_REG register
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* Key Manager interrupt clear register.
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*/
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#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
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/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the km_prep_done_int interrupt
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*/
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#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
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#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
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#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
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#define KEYMNG_PREP_DONE_INT_CLR_S 0
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/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the km_proc_done_int interrupt
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*/
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#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
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#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
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#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
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#define KEYMNG_PROC_DONE_INT_CLR_S 1
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/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the km_post_done_int interrupt
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*/
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#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
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#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
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#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
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#define KEYMNG_POST_DONE_INT_CLR_S 2
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/** KEYMNG_STATIC_REG register
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* Key Manager static configuration register
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*/
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#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
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/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ;bitpos:[1] ;default: 1'd0 ; */
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/*description: Set this bit to choose efuse key instead of key manager deployed key for xts_key.*/
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#define KEYMNG_USE_EFUSE_KEY_XTS (BIT(1))
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#define KEYMNG_USE_EFUSE_KEY_XTS_M ((KEYMNG_USE_EFUSE_KEY_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_XTS_S))
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#define KEYMNG_USE_EFUSE_KEY_XTS_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_XTS_S 1
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/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa_key.*/
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#define KEYMNG_USE_EFUSE_KEY_ECDSA (BIT(0))
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S))
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_ECDSA_S 0
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/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
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* The core clock cycle number to sample one rng input data. Please set it bigger than
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* the clock cycle ratio: T_rng/T_km
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*/
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#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
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#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
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#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
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#define KEYMNG_RND_SWITCH_CYCLE_S 4
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/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
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* Set this bit to use software written init key instead of efuse_init_key.
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*/
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#define KEYMNG_USE_SW_INIT_KEY (BIT(9))
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#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
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#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
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#define KEYMNG_USE_SW_INIT_KEY_S 9
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/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
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* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
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* xts-aes-128.
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*/
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#define KEYMNG_XTS_AES_KEY_LEN (BIT(10))
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#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
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#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U
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#define KEYMNG_XTS_AES_KEY_LEN_S 10
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/** KEYMNG_LOCK_REG register
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* Key Manager static configuration locker register
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*/
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#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
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/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ; bitpos:[1] ; default: 1'd0 ; */
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/* description: Set thus bit to choose efuse key instead of key manager deployed key for xts_key */
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#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS (BIT(1))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_M ((KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S 1
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/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W ; bitpos:[0] ; default: 1'd0 ; */
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/* description: Write 1 to lock ecdsa-key */
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA (BIT(0))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S))
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x1
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#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S 0
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/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
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* Write 1 to lock reg_rnd_switch_cycle.
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*/
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4))
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
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#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4
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/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
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* Write 1 to lock reg_use_sw_init_key.
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*/
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#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5))
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#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
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#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
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#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5
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/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
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* Write 1 to lock reg_xts_aes_key_len.
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*/
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#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6))
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#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
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#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U
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#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6
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/** KEYMNG_CONF_REG register
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* Key Manager configuration register
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*/
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#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
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/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
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* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
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* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
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*/
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#define KEYMNG_KGEN_MODE 0x00000007U
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#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
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#define KEYMNG_KGEN_MODE_V 0x00000007U
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#define KEYMNG_KGEN_MODE_S 0
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/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
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* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
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* xts_256_2_key. 4. xts_128_key. others: reserved.
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*/
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#define KEYMNG_KEY_PURPOSE 0x0000000FU
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#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
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#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
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#define KEYMNG_KEY_PURPOSE_S 3
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/** KEYMNG_START_REG register
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* Key Manager control register
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*/
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#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
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/** KEYMNG_START : WT; bitpos: [0]; default: 0;
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* Write 1 to continue Key Manager operation at LOAD/GAIN state.
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*/
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#define KEYMNG_START (BIT(0))
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#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
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#define KEYMNG_START_V 0x00000001U
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#define KEYMNG_START_S 0
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/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
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* Write 1 to start Key Manager at IDLE state.
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*/
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#define KEYMNG_CONTINUE (BIT(1))
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#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
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#define KEYMNG_CONTINUE_V 0x00000001U
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#define KEYMNG_CONTINUE_S 1
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/** KEYMNG_STATE_REG register
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* Key Manager state register
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*/
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#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
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/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
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* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
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*/
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#define KEYMNG_STATE 0x00000003U
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#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
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#define KEYMNG_STATE_V 0x00000003U
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#define KEYMNG_STATE_S 0
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/** KEYMNG_RESULT_REG register
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* Key Manager operation result register
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*/
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#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
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/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
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* The procedure result bit of Key Manager, only valid when Key Manager procedure is
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* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
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*/
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#define KEYMNG_PROC_RESULT (BIT(0))
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#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
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#define KEYMNG_PROC_RESULT_V 0x00000001U
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#define KEYMNG_PROC_RESULT_S 0
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/** KEYMNG_KEY_VLD_REG register
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* Key Manager key status register
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*/
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#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
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/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
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* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
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* has not been deployed yet.
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*/
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#define KEYMNG_KEY_ECDSA_VLD (BIT(0))
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#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
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#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U
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#define KEYMNG_KEY_ECDSA_VLD_S 0
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/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
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* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
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* key has not been deployed yet.
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*/
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#define KEYMNG_KEY_XTS_VLD (BIT(1))
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#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
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#define KEYMNG_KEY_XTS_VLD_V 0x00000001U
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#define KEYMNG_KEY_XTS_VLD_S 1
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/** KEYMNG_HUK_VLD_REG register
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* Key Manager HUK status register
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*/
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#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
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/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
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* The HUK status. 0: HUK is not valid. 1: HUK is valid.
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*/
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#define KEYMNG_HUK_VALID (BIT(0))
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#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
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#define KEYMNG_HUK_VALID_V 0x00000001U
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#define KEYMNG_HUK_VALID_S 0
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/** KEYMNG_DATE_REG register
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* Version control register
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*/
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#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
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/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
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* Key Manager version control register.
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*/
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#define KEYMNG_DATE 0x0FFFFFFFU
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#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
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#define KEYMNG_DATE_V 0x0FFFFFFFU
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#define KEYMNG_DATE_S 0
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/** KEYMNG_ASSIST_INFO_MEM register
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* The memory that stores assist key info.
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*/
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#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
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#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
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/** KEYMNG_PUBLIC_INFO_MEM register
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* The memory that stores public key info.
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*/
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#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
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#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
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/** KEYMNG_SW_INIT_KEY_MEM register
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* The memory that stores software written init key.
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*/
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#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
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#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
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#ifdef __cplusplus
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}
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#endif
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