mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
409 lines
11 KiB
C
409 lines
11 KiB
C
/*
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Tests for the spi_master device driver
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*/
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#include <esp_types.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <malloc.h>
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#include <string.h>
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#include "rom/ets_sys.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "unity.h"
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#include "driver/spi_master.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_struct.h"
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#include "esp_heap_caps.h"
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static void check_spi_pre_n_for(int clk, int pre, int n)
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{
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esp_err_t ret;
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spi_device_handle_t handle;
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spi_device_interface_config_t devcfg={
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.command_bits=0,
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.address_bits=0,
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.dummy_bits=0,
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.clock_speed_hz=clk,
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.duty_cycle_pos=128,
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.mode=0,
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.spics_io_num=21,
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.queue_size=3
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};
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char sendbuf[16]="";
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spi_transaction_t t;
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memset(&t, 0, sizeof(t));
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ret=spi_bus_add_device(HSPI_HOST, &devcfg, &handle);
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TEST_ASSERT(ret==ESP_OK);
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t.length=16*8;
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t.tx_buffer=sendbuf;
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ret=spi_device_transmit(handle, &t);
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printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, SPI2.clock.clkdiv_pre+1, SPI2.clock.clkcnt_n+1);
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TEST_ASSERT(SPI2.clock.clkcnt_n+1==n);
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TEST_ASSERT(SPI2.clock.clkdiv_pre+1==pre);
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ret=spi_bus_remove_device(handle);
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TEST_ASSERT(ret==ESP_OK);
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}
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TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
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{
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spi_bus_config_t buscfg={
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.mosi_io_num=4,
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.miso_io_num=26,
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.sclk_io_num=25,
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.quadwp_io_num=-1,
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.quadhd_io_num=-1
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};
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esp_err_t ret;
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ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1);
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TEST_ASSERT(ret==ESP_OK);
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check_spi_pre_n_for(26000000, 1, 3);
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check_spi_pre_n_for(20000000, 1, 4);
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check_spi_pre_n_for(8000000, 1, 10);
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check_spi_pre_n_for(800000, 2, 50);
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check_spi_pre_n_for(100000, 16, 50);
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check_spi_pre_n_for(333333, 4, 60);
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check_spi_pre_n_for(900000, 2, 44);
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check_spi_pre_n_for(1, 8192, 64); //Actually should generate the minimum clock speed, 152Hz
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check_spi_pre_n_for(26000000, 1, 3);
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ret=spi_bus_free(HSPI_HOST);
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TEST_ASSERT(ret==ESP_OK);
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}
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static spi_device_handle_t setup_spi_bus(int clkspeed, bool dma) {
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spi_bus_config_t buscfg={
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.mosi_io_num=4,
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.miso_io_num=26,
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.sclk_io_num=25,
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.quadwp_io_num=-1,
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.quadhd_io_num=-1,
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.max_transfer_sz=4096*3
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};
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spi_device_interface_config_t devcfg={
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.command_bits=0,
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.address_bits=0,
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.dummy_bits=0,
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.clock_speed_hz=clkspeed,
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.duty_cycle_pos=128,
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.mode=0,
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.spics_io_num=21,
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.queue_size=3,
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};
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esp_err_t ret;
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spi_device_handle_t handle;
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printf("THIS TEST NEEDS A JUMPER BETWEEN IO4 AND IO26\n");
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ret=spi_bus_initialize(HSPI_HOST, &buscfg, dma?1:0);
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TEST_ASSERT(ret==ESP_OK);
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ret=spi_bus_add_device(HSPI_HOST, &devcfg, &handle);
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TEST_ASSERT(ret==ESP_OK);
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printf("Bus/dev inited.\n");
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return handle;
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}
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static void spi_test(spi_device_handle_t handle, int num_bytes) {
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esp_err_t ret;
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int x;
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srand(num_bytes);
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char *sendbuf=heap_caps_malloc(num_bytes, MALLOC_CAP_DMA);
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char *recvbuf=heap_caps_malloc(num_bytes, MALLOC_CAP_DMA);
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for (x=0; x<num_bytes; x++) {
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sendbuf[x]=rand()&0xff;
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recvbuf[x]=0x55;
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}
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spi_transaction_t t;
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memset(&t, 0, sizeof(t));
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t.length=num_bytes*8;
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t.tx_buffer=sendbuf;
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t.rx_buffer=recvbuf;
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t.addr=0xA00000000000000FL;
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t.command=0x55;
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printf("Transmitting %d bytes...\n", num_bytes);
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ret=spi_device_transmit(handle, &t);
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TEST_ASSERT(ret==ESP_OK);
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srand(num_bytes);
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for (x=0; x<num_bytes; x++) {
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if (sendbuf[x]!=(rand()&0xff)) {
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printf("Huh? Sendbuf corrupted at byte %d\n", x);
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TEST_ASSERT(0);
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}
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if (sendbuf[x]!=recvbuf[x]) break;
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}
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if (x!=num_bytes) {
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int from=x-16;
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if (from<0) from=0;
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printf("Error at %d! Sent vs recved: (starting from %d)\n" , x, from);
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for (int i=0; i<32; i++) {
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if (i+from<num_bytes) printf("%02X ", sendbuf[from+i]);
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}
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printf("\n");
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for (int i=0; i<32; i++) {
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if (i+from<num_bytes) printf("%02X ", recvbuf[from+i]);
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}
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printf("\n");
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// TEST_ASSERT(0);
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}
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printf("Success!\n");
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free(sendbuf);
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free(recvbuf);
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}
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static void destroy_spi_bus(spi_device_handle_t handle) {
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esp_err_t ret;
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ret=spi_bus_remove_device(handle);
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TEST_ASSERT(ret==ESP_OK);
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ret=spi_bus_free(HSPI_HOST);
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TEST_ASSERT(ret==ESP_OK);
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}
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#define TEST_LEN 111
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TEST_CASE("SPI Master test", "[spi][ignore]")
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{
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printf("Testing bus at 80KHz\n");
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spi_device_handle_t handle=setup_spi_bus(80000, true);
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spi_test(handle, 16); //small
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spi_test(handle, 21); //small, unaligned
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spi_test(handle, 36); //aligned
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spi_test(handle, 128); //aligned
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spi_test(handle, 129); //unaligned
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spi_test(handle, 4096-2); //multiple descs, edge case 1
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spi_test(handle, 4096-1); //multiple descs, edge case 2
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spi_test(handle, 4096*3); //multiple descs
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destroy_spi_bus(handle);
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printf("Testing bus at 80KHz, non-DMA\n");
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handle=setup_spi_bus(80000, false);
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spi_test(handle, 4); //aligned
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spi_test(handle, 16); //small
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spi_test(handle, 21); //small, unaligned
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destroy_spi_bus(handle);
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printf("Testing bus at 26MHz\n");
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handle=setup_spi_bus(20000000, true);
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spi_test(handle, 128); //DMA, aligned
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spi_test(handle, 4096*3); //DMA, multiple descs
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destroy_spi_bus(handle);
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printf("Testing bus at 900KHz\n");
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handle=setup_spi_bus(9000000, true);
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spi_test(handle, 128); //DMA, aligned
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spi_test(handle, 4096*3); //DMA, multiple descs
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destroy_spi_bus(handle);
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}
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TEST_CASE("SPI Master test, interaction of multiple devs", "[spi][ignore]") {
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esp_err_t ret;
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spi_device_interface_config_t devcfg={
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.command_bits=0,
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.address_bits=0,
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.dummy_bits=0,
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.clock_speed_hz=1000000,
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.duty_cycle_pos=128,
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.mode=0,
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.spics_io_num=23,
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.queue_size=3,
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};
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spi_device_handle_t handle1=setup_spi_bus(80000, true);
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spi_device_handle_t handle2;
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spi_bus_add_device(HSPI_HOST, &devcfg, &handle2);
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printf("Sending to dev 1\n");
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spi_test(handle1, 7);
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printf("Sending to dev 1\n");
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spi_test(handle1, 15);
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printf("Sending to dev 2\n");
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spi_test(handle2, 15);
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printf("Sending to dev 1\n");
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spi_test(handle1, 32);
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printf("Sending to dev 2\n");
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spi_test(handle2, 32);
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printf("Sending to dev 1\n");
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spi_test(handle1, 63);
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printf("Sending to dev 2\n");
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spi_test(handle2, 63);
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printf("Sending to dev 1\n");
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spi_test(handle1, 5000);
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printf("Sending to dev 2\n");
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spi_test(handle2, 5000);
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ret=spi_bus_remove_device(handle2);
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TEST_ASSERT(ret==ESP_OK);
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destroy_spi_bus(handle1);
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}
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TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)", "[spi]")
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{
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//spi config
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spi_bus_config_t bus_config;
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spi_device_interface_config_t device_config;
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spi_device_handle_t spi;
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spi_host_device_t host;
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int dma = 1;
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memset(&bus_config, 0, sizeof(spi_bus_config_t));
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memset(&device_config, 0, sizeof(spi_device_interface_config_t));
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bus_config.miso_io_num = -1;
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bus_config.mosi_io_num = 26;
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bus_config.sclk_io_num = 25;
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bus_config.quadwp_io_num = -1;
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bus_config.quadhd_io_num = -1;
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device_config.clock_speed_hz = 50000;
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device_config.mode = 0;
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device_config.spics_io_num = -1;
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device_config.queue_size = 1;
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device_config.flags = SPI_DEVICE_TXBIT_LSBFIRST | SPI_DEVICE_RXBIT_LSBFIRST;
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struct spi_transaction_t transaction = {
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.flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA,
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.length = 16,
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.tx_buffer = NULL,
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.rx_buffer = NULL,
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.tx_data = {0x04, 0x00}
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};
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//initialize for first host
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host = 1;
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assert(spi_bus_initialize(host, &bus_config, dma) == ESP_OK);
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assert(spi_bus_add_device(host, &device_config, &spi) == ESP_OK);
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printf("before first xmit\n");
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assert(spi_device_transmit(spi, &transaction) == ESP_OK);
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printf("after first xmit\n");
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assert(spi_bus_remove_device(spi) == ESP_OK);
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assert(spi_bus_free(host) == ESP_OK);
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//for second host and failed before
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host = 2;
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assert(spi_bus_initialize(host, &bus_config, dma) == ESP_OK);
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assert(spi_bus_add_device(host, &device_config, &spi) == ESP_OK);
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printf("before second xmit\n");
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// the original version (bit mis-written) stucks here.
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assert(spi_device_transmit(spi, &transaction) == ESP_OK);
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// test case success when see this.
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printf("after second xmit\n");
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}
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IRAM_ATTR static uint32_t data_iram[320];
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DRAM_ATTR static uint32_t data_dram[320];
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//force to place in code area.
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static const uint32_t data_drom[320] = {0};
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#define PIN_NUM_MISO 25
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#define PIN_NUM_MOSI 23
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#define PIN_NUM_CLK 19
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#define PIN_NUM_CS 22
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#define PIN_NUM_DC 21
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#define PIN_NUM_RST 18
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#define PIN_NUM_BCKL 5
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TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
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{
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uint32_t data_rxdram[320];
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esp_err_t ret;
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spi_device_handle_t spi;
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spi_bus_config_t buscfg={
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.miso_io_num=PIN_NUM_MISO,
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.mosi_io_num=PIN_NUM_MOSI,
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.sclk_io_num=PIN_NUM_CLK,
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.quadwp_io_num=-1,
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.quadhd_io_num=-1
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};
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spi_device_interface_config_t devcfg={
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.clock_speed_hz=10000000, //Clock out at 10 MHz
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.mode=0, //SPI mode 0
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.spics_io_num=PIN_NUM_CS, //CS pin
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.queue_size=7, //We want to be able to queue 7 transactions at a time
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.pre_cb=NULL, //Specify pre-transfer callback to handle D/C line
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};
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//Initialize the SPI bus
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ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1);
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assert(ret==ESP_OK);
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//Attach the LCD to the SPI bus
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ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi);
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assert(ret==ESP_OK);
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static spi_transaction_t trans[6];
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int x;
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printf("iram: %p, dram: %p, drom: %p\n", data_iram, data_dram, data_drom);
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memset(trans, 0, 6*sizeof(spi_transaction_t));
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trans[0].length = 320*8,
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trans[0].tx_buffer = data_iram;
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trans[0].rx_buffer = data_rxdram;
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trans[1].length = 320*8,
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trans[1].tx_buffer = data_dram;
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trans[1].rx_buffer = data_rxdram;
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trans[2].length = 320*8,
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trans[2].tx_buffer = data_drom;
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trans[2].rx_buffer = data_rxdram;
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trans[3].length = 320*8,
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trans[3].tx_buffer = data_drom;
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trans[3].rx_buffer = data_iram;
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trans[4].length = 320*8,
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trans[4].rxlength = 8*4;
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trans[4].tx_buffer = data_drom;
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trans[4].flags = SPI_TRANS_USE_RXDATA;
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trans[5].length = 8*4;
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trans[5].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA;
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//Queue all transactions.
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for (x=0; x<6; x++) {
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ret=spi_device_queue_trans(spi,&trans[x], portMAX_DELAY);
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assert(ret==ESP_OK);
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}
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for (x=0; x<6; x++) {
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spi_transaction_t* ptr;
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ret=spi_device_get_trans_result(spi,&ptr, portMAX_DELAY);
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assert(ret==ESP_OK);
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assert(ptr = trans+x);
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}
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}
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