mirror of
https://github.com/espressif/esp-idf.git
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120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdarg.h>
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#include "sdkconfig.h"
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#include "esp_flash.h"
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#include "esp_attr.h"
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#include "esp_rom_sys.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/ets_sys.h"
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#include "esp32s3/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/ets_sys.h"
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#include "esp32c3/rom/cache.h"
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#endif
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#include "esp_attr.h"
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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typedef struct {
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uint32_t icache_autoload;
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uint32_t dcache_autoload;
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} spi_noos_arg_t;
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static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
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#elif CONFIG_IDF_TARGET_ESP32C3
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typedef struct {
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uint32_t icache_autoload;
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} spi_noos_arg_t;
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static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
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#endif
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static IRAM_ATTR esp_err_t start(void *arg)
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{
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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spi_noos_arg_t *spi_arg = arg;
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spi_arg->icache_autoload = Cache_Suspend_ICache();
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spi_arg->dcache_autoload = Cache_Suspend_DCache();
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#elif CONFIG_IDF_TARGET_ESP32C3
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spi_noos_arg_t *spi_arg = arg;
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spi_arg->icache_autoload = Cache_Suspend_ICache();
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#endif
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t end(void *arg)
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{
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Flush(0);
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Cache_Flush(1);
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Cache_Read_Enable(0);
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Cache_Read_Enable(1);
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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spi_noos_arg_t *spi_arg = arg;
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Cache_Invalidate_ICache_All();
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Cache_Resume_ICache(spi_arg->icache_autoload);
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Cache_Resume_DCache(spi_arg->dcache_autoload);
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#elif CONFIG_IDF_TARGET_ESP32C3
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spi_noos_arg_t *spi_arg = arg;
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Cache_Invalidate_ICache_All();
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Cache_Resume_ICache(spi_arg->icache_autoload);
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#endif
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t delay_us(void *arg, uint32_t us)
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{
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esp_rom_delay_us(us);
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return ESP_OK;
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}
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// Currently when the os is not up yet, the caller is supposed to call esp_flash APIs with proper
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// buffers.
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IRAM_ATTR void* get_temp_buffer_not_supported(void* arg, size_t reqest_size, size_t* out_size)
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{
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return NULL;
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}
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const DRAM_ATTR esp_flash_os_functions_t esp_flash_noos_functions = {
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.start = start,
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.end = end,
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.delay_us = delay_us,
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.region_protected = NULL,
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/* the caller is supposed to call esp_flash_read/esp_flash_write APIs with buffers in DRAM */
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.get_temp_buffer = NULL,
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.release_temp_buffer = NULL,
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.yield = NULL,
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};
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esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip)
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{
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chip->os_func = &esp_flash_noos_functions;
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#if !CONFIG_IDF_TARGET_ESP32
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chip->os_func_data = &spi_arg;
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#endif
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return ESP_OK;
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}
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