harshal.patil 0868604664
fix(esp_hw_support): Fix incorrect PMA configuration for ESP32-P4
- As the PMA entry that made some memory regions cacheable was
assigned the highest priority, some intermediate inaccessible
memory regions bypassed protection.

- Added tests for the same

- Verified that even after changing the priority of the PMA entry,
a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address)
still needs the same number (29) of CPU cycles.
2024-06-11 12:23:06 +05:30
..
2022-08-01 15:52:21 +08:00
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2023-10-16 10:23:09 +02:00