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c331c85318
For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required. Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be cleared. When system clock switches up, the delays should be restored.
256 lines
12 KiB
C
256 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "esp_flash_partitions.h"
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "mspi_timing_tuning_configs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPI_TIMING_CONFIG_NUM_DEFAULT 20 //This should be larger than the max available timing config num
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#define SPI_TIMING_TEST_DATA_LEN 64
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#define SPI_TIMING_PSRAM_TEST_DATA_ADDR 0
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#define SPI_TIMING_FLASH_TEST_DATA_ADDR ESP_BOOTLOADER_OFFSET
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/**
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* @note BACKGOURND:
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*
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* The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock:
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*
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* PLL ----| |---- FLASH Module Clock
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* XTAL ----|----> Core Clock ---->|
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* RTC8M ----| |---- PSRAM Module Clock
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*
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*
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* DDR stands for double data rate, MSPI samples at both posedge and negedge. So the real spped will be doubled.
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* Speed from high to low: 120M DDR > 80M DDR > 120 SDR > 80M SDR > ...
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*
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* Module with speed lower than 120M SDR doesn't need to be tuned
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*
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* @note LIMITATION:
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* How to determine the core clock on 728. There are 2 limitations.
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*
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* 1. MSPI FLASH and PSRAM share the core clock register. Therefore:
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* SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
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*
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* 2. DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2.
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*/
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//--------------------------------------FLASH Sampling Mode --------------------------------------//
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#define SPI_TIMING_FLASH_DTR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
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#define SPI_TIMING_FLASH_STR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
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//--------------------------------------FLASH Module Clock --------------------------------------//
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#if CONFIG_ESPTOOLPY_FLASHFREQ_20M
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#define SPI_TIMING_FLASH_MODULE_CLOCK 20
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
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#define SPI_TIMING_FLASH_MODULE_CLOCK 40
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define SPI_TIMING_FLASH_MODULE_CLOCK 80
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#else //CONFIG_ESPTOOLPY_FLASHFREQ_120M
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#define SPI_TIMING_FLASH_MODULE_CLOCK 120
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#endif
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//------------------------------------FLASH Needs Tuning or not-------------------------------------//
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#if SPI_TIMING_FLASH_DTR_MODE
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#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 40)
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#elif SPI_TIMING_FLASH_STR_MODE
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#define SPI_TIMING_FLASH_NEEDS_TUNING (SPI_TIMING_FLASH_MODULE_CLOCK > 80)
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#endif
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//--------------------------------------PSRAM Sampling Mode --------------------------------------//
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#define SPI_TIMING_PSRAM_DTR_MODE CONFIG_SPIRAM_MODE_OCT
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#define SPI_TIMING_PSRAM_STR_MODE !CONFIG_SPIRAM_MODE_OCT
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//--------------------------------------PSRAM Module Clock --------------------------------------//
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#if CONFIG_ESP32S3_SPIRAM_SUPPORT
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#if CONFIG_SPIRAM_SPEED_40M
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#define SPI_TIMING_PSRAM_MODULE_CLOCK 40
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#elif CONFIG_SPIRAM_SPEED_80M
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#define SPI_TIMING_PSRAM_MODULE_CLOCK 80
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#else //CONFIG_SPIRAM_SPEED_120M
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#define SPI_TIMING_PSRAM_MODULE_CLOCK 120
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#endif
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#else //Disable PSRAM
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#define SPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz, because we rely on `SPI_TIMING_PSRAM_MODULE_CLOCK` macro for calculation and check below, see `Determine the Core Clock` chapter
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#endif
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//------------------------------------PSRAM Needs Tuning or not-------------------------------------//
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#if SPI_TIMING_PSRAM_DTR_MODE
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#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 40)
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#elif SPI_TIMING_PSRAM_STR_MODE
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#define SPI_TIMING_PSRAM_NEEDS_TUNING (SPI_TIMING_PSRAM_MODULE_CLOCK > 80)
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#endif
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/**
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* @note Define A feasible core clock below: SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ and SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
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*/
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/**
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* Due to MSPI core clock is used by both MSPI Flash and PSRAM clock,
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* define the STR/DTR mode here for selecting the core clock:
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* @note If either Flash or PSRAM, or both of them are set to DTR mode, then we use DIV 2
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*/
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#if (SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE)
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#define SPI_TIMING_CORE_CLOCK_DIV 2
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#else //#if (SPI_TIMING_FLASH_STR_MODE && (SPI_TIMING_PSRAM_STR_MODE || !CONFIG_ESP32S3_SPIRAM_SUPPORT))
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#define SPI_TIMING_CORE_CLOCK_DIV 1
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#endif
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///////////////////////////////////// FLASH CORE CLOCK /////////////////////////////////////
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//FLASH 80M DTR
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#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 160
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#endif
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//FLASH 120M DTR
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#if SPI_TIMING_FLASH_DTR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
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#endif
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//FLASH 120M STR
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#if SPI_TIMING_FLASH_STR_MODE && CONFIG_ESPTOOLPY_FLASHFREQ_120M
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#if (SPI_TIMING_CORE_CLOCK_DIV == 2)
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
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#elif (SPI_TIMING_CORE_CLOCK_DIV == 1)
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#define SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 120
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#endif
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#endif //FLASH 120M STR
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///////////////////////////////////// PSRAM CORE CLOCK /////////////////////////////////////
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//PSRAM 80M DTR
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#if SPI_TIMING_PSRAM_DTR_MODE && CONFIG_SPIRAM_SPEED_80M
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#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 160
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#endif
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//PSRAM 120M STR
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#if SPI_TIMING_PSRAM_STR_MODE && CONFIG_SPIRAM_SPEED_120M
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#if (SPI_TIMING_CORE_CLOCK_DIV == 2)
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#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240
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#elif (SPI_TIMING_CORE_CLOCK_DIV == 1)
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#define SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 120
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#endif
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#endif //PSRAM 120M STR
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//------------------------------------------Determine the Core Clock-----------------------------------------------//
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/**
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* @note
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* Limitation 1:
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* On 728, MSPI FLASH and PSRAM share the core clock register. Therefore,
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* the expected CORE CLOCK frequencies should be the same.
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*/
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#if SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
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_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported");
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#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
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//If only FLASH needs tuning, the core clock COULD be as FLASH expected
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#elif SPI_TIMING_FLASH_NEEDS_TUNING && !SPI_TIMING_PSRAM_NEEDS_TUNING
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_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
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#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
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//If only PSRAM needs tuning, the core clock COULD be as PSRAM expected
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#elif !SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
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_Static_assert(SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
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#define SPI_TIMING_CORE_CLOCK_MHZ SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
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#else
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#define SPI_TIMING_CORE_CLOCK_MHZ 80
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#endif
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/**
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* @note
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* Limitation 2: DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2.
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*/
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#define CHECK_POWER_OF_2(n) ((((n) & ((~(n)) + 1))) == (n))
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#if SPI_TIMING_FLASH_DTR_MODE
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_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_FLASH_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported");
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#endif
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#if SPI_TIMING_PSRAM_DTR_MODE
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_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported");
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#endif
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//------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------//
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#define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
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(spi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
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.available_config_num = MSPI_TIMING_##type##_CONFIG_NUM_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
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.default_config_id = MSPI_TIMING_##type##_DEFAULT_CONFIG_ID_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode }
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#define _GET_TUNING_CONFIG(type, core_clock, module_clock, mode) __GET_TUNING_CONFIG(type, core_clock, module_clock, mode)
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#define SPI_TIMING_FLASH_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(FLASH, core_clock_mhz, module_clock_mhz, mode)
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#define SPI_TIMING_PSRAM_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(PSRAM, core_clock_mhz, module_clock_mhz, mode)
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/**
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* SPI timing tuning registers. The macro `SPI_TIMING_FLASH_CONFIG_TABLE` below is the corresponding register value table.
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* Upper layer rely on these 3 registers to tune the timing.
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*/
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typedef struct {
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uint8_t spi_din_mode; /*!< input signal delay mode*/
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uint8_t spi_din_num; /*!< input signal delay number */
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uint8_t extra_dummy_len; /*!< extra dummy length*/
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} spi_timing_tuning_param_t;
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typedef struct {
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spi_timing_tuning_param_t tuning_config_table[SPI_TIMING_CONFIG_NUM_DEFAULT]; //available timing tuning configs
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uint32_t available_config_num;
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uint32_t default_config_id; //If tuning fails, we use this one as default
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} spi_timing_config_t;
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/**
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* The SPI FLASH module clock and SPI PSRAM module clock is divided from the SPI core clock, core clock is from system clock:
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*
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* PLL ----| |---- FLASH Module Clock
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* XTAL ----|----> Core Clock ---->|
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* RTC8M ----| |---- PSRAM Module Clock
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*
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*/
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typedef enum {
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SPI_TIMING_CONFIG_CORE_CLOCK_80M,
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SPI_TIMING_CONFIG_CORE_CLOCK_120M,
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SPI_TIMING_CONFIG_CORE_CLOCK_160M,
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SPI_TIMING_CONFIG_CORE_CLOCK_240M
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} spi_timing_config_core_clock_t;
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spi_timing_config_core_clock_t spi_timing_config_get_core_clock(void);
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void spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock);
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void spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv);
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void spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num);
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void spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy);
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void spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len);
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void spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv);
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void spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num);
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void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy);
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void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len);
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void spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t *buf, uint32_t addr, uint32_t len);
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/*-------------------------------------------------------------------------------------------------
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* SPI1 Timing Tuning APIs
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* These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for
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* configuring SPI1 timing tuning related registers to find best tuning parameter
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*-------------------------------------------------------------------------------------------------*/
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void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num);
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void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy);
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void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num);
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void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy);
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/**
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* SPI1 register info get APIs. These APIs inform `spi_flash_timing_tuning.c` (driver layer) of the SPI1 flash settings.
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* In this way, other components (e.g.: esp_flash driver) can get the info from it (`spi_flash_timing_tuning.c`).
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*/
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void spi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time);
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uint32_t spi_timing_config_get_flash_clock_reg(void);
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#ifdef __cplusplus
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}
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#endif
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