mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
26a3cb93c7
1. move dport access header files to soc 2. reduce dport register write protection. Only protect read operation
295 lines
9.9 KiB
C
295 lines
9.9 KiB
C
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#include <esp_types.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "rom/ets_sys.h"
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#include "rom/lldesc.h"
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#include "rom/gpio.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "unity.h"
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#include "soc/uart_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/gpio_reg.h"
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#include "soc/i2s_reg.h"
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#define DPORT_I2S0_CLK_EN (BIT(4))
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#define DPORT_I2S0_RST (BIT(4))
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/*
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This test tests the s32c1i instruction when the AHB bus is also used. To create some AHB traffic, we use the I2S interface
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to copy bytes over from one memory location to another. DO NOT USE the i2s routines inhere, they've been trial-and-error'ed until
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the point where they happened to do what I want.
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*/
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static void lcdIfaceInit()
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{
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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//Init pins to i2s functions
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SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO5_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO18_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO20_U, 0);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
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WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S));
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WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS
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WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S));
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// WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG, (I2S0O_BCK_OUT_IDX<<GPIO_GPIO_FUNC0_OUT_SEL_S));
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//GPIO_SET_GPIO_FUNC11_OUT_INV_SEL(1); //old
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WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, READ_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG) | GPIO_FUNC11_OUT_INV_SEL);
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//Reset I2S subsystem
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
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WRITE_PERI_REG(I2S_CONF_REG(0), 0);//I2S_SIG_LOOPBACK);
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WRITE_PERI_REG(I2S_CONF2_REG(0), 0);
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WRITE_PERI_REG(I2S_SAMPLE_RATE_CONF_REG(0),
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(16 << I2S_RX_BITS_MOD_S) |
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(16 << I2S_TX_BITS_MOD_S) |
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(1 << I2S_RX_BCK_DIV_NUM_S) |
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(1 << I2S_TX_BCK_DIV_NUM_S));
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WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),
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I2S_CLKA_ENA | I2S_CLK_EN |
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(1 << I2S_CLKM_DIV_A_S) |
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(1 << I2S_CLKM_DIV_B_S) |
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(1 << I2S_CLKM_DIV_NUM_S));
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WRITE_PERI_REG(I2S_FIFO_CONF_REG(0),
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(32 << I2S_TX_DATA_NUM_S) | //Low watermark for IRQ
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(32 << I2S_RX_DATA_NUM_S));
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WRITE_PERI_REG(I2S_CONF1_REG(0), I2S_RX_PCM_BYPASS | I2S_TX_PCM_BYPASS);
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WRITE_PERI_REG(I2S_CONF_CHAN_REG(0), (2 << I2S_TX_CHAN_MOD_S) | (2 << I2S_RX_CHAN_MOD_S));
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//Invert WS to active-low
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RIGHT_FIRST | I2S_RX_RIGHT_FIRST);
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WRITE_PERI_REG(I2S_TIMING_REG(0), 0);
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}
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static volatile lldesc_t dmaDesc[2];
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static void finishDma()
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{
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//No need to finish if no DMA transfer going on
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if (!(READ_PERI_REG(I2S_FIFO_CONF_REG(0))&I2S_DSCR_EN)) {
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return;
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}
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//Wait till fifo done
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while (!(READ_PERI_REG(I2S_INT_RAW_REG(0))&I2S_TX_REMPTY_INT_RAW)) ;
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//Wait for last bytes to leave i2s xmit thing
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//ToDo: poll bit in next hw
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// for (i=0; i<(1<<8); i++);
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while (!(READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_IDLE));
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//Reset I2S for next transfer
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_START | I2S_RX_START);
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CLEAR_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_START | I2S_INLINK_START);
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
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// for (i=0; i<(1<<8); i++);
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while ((READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_FIFO_RESET_BACK));
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}
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/*
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This is a very, very, very hacked up LCD routine which ends up basically doing a memcpy from sbuf to rbuf.
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*/
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static void sendRecvBufDma(uint16_t *sbuf, uint16_t *rbuf, int len)
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{
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//Fill DMA descriptor
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dmaDesc[0].length = len * 2;
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dmaDesc[0].size = len * 2;
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dmaDesc[0].owner = 1;
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dmaDesc[0].sosf = 0;
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dmaDesc[0].buf = (uint8_t *)sbuf;
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dmaDesc[0].offset = 0; //unused in hw
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dmaDesc[0].empty = 0;
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dmaDesc[0].eof = 1;
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dmaDesc[1].length = len * 2;
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dmaDesc[1].size = len * 2;
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dmaDesc[1].owner = 1;
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dmaDesc[1].sosf = 0;
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dmaDesc[1].buf = (uint8_t *)rbuf;
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dmaDesc[1].offset = 0; //unused in hw
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dmaDesc[1].empty = 0;
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dmaDesc[1].eof = 1;
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//Reset DMA
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SET_PERI_REG_MASK(I2S_LC_CONF_REG(0), I2S_IN_RST | I2S_OUT_RST | I2S_AHBM_RST | I2S_AHBM_FIFO_RST);
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CLEAR_PERI_REG_MASK(I2S_LC_CONF_REG(0), I2S_IN_RST | I2S_OUT_RST | I2S_AHBM_RST | I2S_AHBM_FIFO_RST);
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//Reset I2S FIFO
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_FIFO_RESET);
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_FIFO_RESET);
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//Set desc addr
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CLEAR_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_ADDR);
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SET_PERI_REG_MASK(I2S_OUT_LINK_REG(0), ((uint32_t)(&dmaDesc[0]))&I2S_OUTLINK_ADDR);
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CLEAR_PERI_REG_MASK(I2S_IN_LINK_REG(0), I2S_INLINK_ADDR);
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SET_PERI_REG_MASK(I2S_IN_LINK_REG(0), ((uint32_t)(&dmaDesc[1]))&I2S_INLINK_ADDR);
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SET_PERI_REG_MASK(I2S_FIFO_CONF_REG(0), I2S_DSCR_EN); //Enable DMA mode
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WRITE_PERI_REG(I2S_RXEOF_NUM_REG(0), len);
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//Enable and configure DMA
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WRITE_PERI_REG(I2S_LC_CONF_REG(0), I2S_OUT_DATA_BURST_EN |
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I2S_OUT_EOF_MODE | I2S_OUTDSCR_BURST_EN | I2S_OUT_DATA_BURST_EN |
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I2S_INDSCR_BURST_EN | I2S_MEM_TRANS_EN);
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//Start transmission
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SET_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_START);
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SET_PERI_REG_MASK(I2S_IN_LINK_REG(0), I2S_INLINK_START);
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_START | I2S_RX_START);
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//Clear int flags
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WRITE_PERI_REG(I2S_INT_CLR_REG(0), 0xFFFFFFFF);
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}
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#define DMALEN (2048-2)
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static void tskLcd(void *pvParameters)
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{
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uint16_t *sbuf = malloc(DMALEN * 2);
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uint16_t *rbuf = malloc(DMALEN * 2);
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uint16_t xorval = 0;
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int x;
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lcdIfaceInit();
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// lcdFlush();
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while (1) {
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for (x = 0; x < DMALEN; x++) {
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sbuf[x] = x ^ xorval;
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}
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for (x = 0; x < DMALEN; x++) {
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rbuf[x] = 0; //clear rbuf
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}
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sendRecvBufDma(sbuf, rbuf, DMALEN);
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vTaskDelay(20 / portTICK_PERIOD_MS);
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finishDma();
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for (x = 0; x < DMALEN; x++) if (rbuf[x] != (x ^ xorval)) {
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printf("Rxbuf err! pos %d val %x xor %x", x, (int)rbuf[x], (int)xorval);
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}
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printf(".");
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fflush(stdout);
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xorval++;
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}
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}
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void test_s32c1i_lock(volatile int *lockvar, int lockval, int unlockval, volatile int *ctr);
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static volatile int ctr = 0, state = 0;
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static volatile int lock = 0;
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static void tskOne(void *pvParameters)
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{
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int x;
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int err = 0, run = 0;
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while (1) {
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ctr = 0; lock = 0;
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state = 1;
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for (x = 0; x < 16 * 1024; x++) {
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test_s32c1i_lock(&lock, 1, 0, &ctr);
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}
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vTaskDelay(60 / portTICK_PERIOD_MS);
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state = 2;
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if (ctr != 16 * 1024 * 2) {
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printf("Lock malfunction detected! Ctr=0x%x instead of %x\n", ctr, 16 * 1024 * 2);
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err++;
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}
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run++;
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printf("Run %d err %d\n", run, err);
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vTaskDelay(20 / portTICK_PERIOD_MS);
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}
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}
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#define FB2ADDR 0x40098000
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static void tskTwo(void *pvParameters)
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{
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int x;
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int *p = (int *)FB2ADDR;
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int *s = (int *)test_s32c1i_lock;
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void (*test_s32c1i_lock2)(volatile int * lockvar, int lockval, int unlockval, volatile int * ctr) = (void *)FB2ADDR;
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volatile int w;
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int delay;
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for (x = 0; x < 100; x++) {
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*p++ = *s++; //copy routine to different pool
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}
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while (1) {
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while (state != 1) ;
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for (x = 0; x < 16 * 1024; x++) {
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test_s32c1i_lock2(&lock, 2, 0, &ctr);
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//Some random delay to increase chance of weirdness
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if ((x & 0x1f) == 0) {
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delay = rand() & 0x1f;
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for (w = 0; w < delay; w++);
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}
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}
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while (state != 2);
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}
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}
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TEST_CASE("S32C1I vs AHB test (needs I2S)", "[hw][ignore]")
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{
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int i;
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TaskHandle_t th[3];
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state = 0;
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printf("Creating tasks\n");
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xTaskCreatePinnedToCore(tskTwo , "tsktwo" , 2048, NULL, 3, &th[1], 1);
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xTaskCreatePinnedToCore(tskOne , "tskone" , 2048, NULL, 3, &th[0], 0);
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xTaskCreatePinnedToCore(tskLcd , "tsklcd" , 2048, NULL, 3, &th[2], 0);
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// Let stuff run for 20s
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while (1) {
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vTaskDelay(20000 / portTICK_PERIOD_MS);
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}
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//Shut down all the tasks
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for (i = 0; i < 3; i++) {
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vTaskDelete(th[i]);
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}
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}
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