mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
9a6de4cb3e
On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions.
23 lines
675 B
C
23 lines
675 B
C
/*
|
|
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
#pragma once
|
|
|
|
#include "soc/soc_caps.h"
|
|
|
|
/* Need a way to signal which core caused the INT WDT like we do with EXCAUSE on xtensa.
|
|
Choosing a large number that is unlikely to conflict with any actual riscv mcauses
|
|
bit 12 and above are always zero on the CPU used by P4
|
|
*/
|
|
#define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM
|
|
#if SOC_CPU_CORES_NUM > 1
|
|
#define PANIC_RSN_INTWDT_CPU1_FLAG (1 << 12)
|
|
#define PANIC_RSN_INTWDT_CPU1 (PANIC_RSN_INTWDT_CPU1_FLAG | ETS_INT_WDT_INUM)
|
|
#endif
|
|
|
|
#define PANIC_RSN_CACHEERR 3
|
|
|
|
#define MCAUSE_ILLEGAL_INSTRUCTION 2
|