mirror of
https://github.com/espressif/esp-idf.git
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2d44dc1eed
This commit gives basic mmu driver framework. Now it is able to maintain mmu virtual address usage on esp32, esp32s2 and esp32s3. Usage to external virtual address should rely on mmu functions to know which address range is available, instead of hardcoded. This commit also improves psram memory that is added to the heap allocator. Now it's added to the heap, according to the memory alignment. Closes https://github.com/espressif/esp-idf/issues/8295
268 lines
9.7 KiB
C
268 lines
9.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This file will be redesigned into MMU driver, to maintain all the external
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* memory contexts including:
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* - Flash
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* - PSRAM
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* - DDR
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*
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* Now only MMU-PSRAM related private APIs
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*/
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#include <stdint.h>
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#include <string.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_check.h"
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#include "soc/soc_caps.h"
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#include "ext_mem_layout.h"
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#include "freertos/FreeRTOS.h"
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#include "hal/cache_types.h"
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#include "hal/cache_ll.h"
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#include "hal/mmu_types.h"
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#include "hal/mmu_ll.h"
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#include "mmu.h"
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#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
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#define MMU_PAGE_SIZE CONFIG_MMU_PAGE_SIZE
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//This flag indicates the memory region is merged, we don't care about it anymore
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#define MEM_REGION_MERGED -1
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static const char *TAG = "mmu";
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extern int _instruction_reserved_start;
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extern int _instruction_reserved_end;
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extern int _rodata_reserved_start;
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extern int _rodata_reserved_end;
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typedef struct mmu_linear_mem_ {
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cache_bus_mask_t bus_id;
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intptr_t start;
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intptr_t end;
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size_t pool_size;
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intptr_t free_head;
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size_t free_size;
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int caps;
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} mmu_linear_mem_t;
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typedef struct {
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/**
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* number of memory regions that are available, after coalescing, this number should be smaller than or equal to `SOC_MMU_LINEAR_ADDRESS_REGION_NUM`
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*/
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uint32_t num_regions;
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/**
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* This saves the available MMU linear address regions,
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* after reserving flash .rodata and .text, and after coalescing.
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* Only the first `num_regions` items are valid
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*/
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mmu_linear_mem_t mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM];
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} mmu_ctx_t;
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static mmu_ctx_t s_mmu_ctx;
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static void s_reserve_irom_region(mmu_linear_mem_t *hw_mem_regions, int region_nums)
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{
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/**
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* We follow the way how 1st bootloader load flash .text:
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*
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* - Now IBUS addresses (between `_instruction_reserved_start` and `_instruction_reserved_end`) are consecutive on all chips,
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* we strongly rely on this to calculate the .text length
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*/
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size_t irom_len_to_reserve = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start;
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assert((mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_start)) == irom_len_to_reserve);
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irom_len_to_reserve = ALIGN_UP_BY(irom_len_to_reserve, MMU_PAGE_SIZE);
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)&_instruction_reserved_start, irom_len_to_reserve);
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for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
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if (bus_mask & hw_mem_regions[i].bus_id) {
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if (hw_mem_regions[i].pool_size <= irom_len_to_reserve) {
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hw_mem_regions[i].free_head = hw_mem_regions[i].end;
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hw_mem_regions[i].free_size = 0;
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irom_len_to_reserve -= hw_mem_regions[i].pool_size;
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} else {
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hw_mem_regions[i].free_head = hw_mem_regions[i].free_head + irom_len_to_reserve;
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hw_mem_regions[i].free_size -= irom_len_to_reserve;
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}
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}
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}
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}
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static void s_reserve_drom_region(mmu_linear_mem_t *hw_mem_regions, int region_nums)
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{
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/**
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* Similarly, we follow the way how 1st bootloader load flash .rodata:
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*/
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size_t drom_len_to_reserve = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start;
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assert((mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_start)) == drom_len_to_reserve);
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drom_len_to_reserve = ALIGN_UP_BY(drom_len_to_reserve, MMU_PAGE_SIZE);
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cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)&_rodata_reserved_start, drom_len_to_reserve);
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for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
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if (bus_mask & hw_mem_regions[i].bus_id) {
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if (hw_mem_regions[i].pool_size <= drom_len_to_reserve) {
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hw_mem_regions[i].free_head = hw_mem_regions[i].end;
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hw_mem_regions[i].free_size = 0;
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drom_len_to_reserve -= hw_mem_regions[i].pool_size;
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} else {
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hw_mem_regions[i].free_head = hw_mem_regions[i].free_head + drom_len_to_reserve;
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hw_mem_regions[i].free_size -= drom_len_to_reserve;
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}
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}
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}
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}
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void esp_mmu_init(void)
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{
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mmu_linear_mem_t hw_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {};
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for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
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hw_mem_regions[i].start = g_mmu_mem_regions[i].start;
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hw_mem_regions[i].end = g_mmu_mem_regions[i].end;
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hw_mem_regions[i].pool_size = g_mmu_mem_regions[i].size;
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hw_mem_regions[i].free_size = g_mmu_mem_regions[i].size;
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hw_mem_regions[i].free_head = g_mmu_mem_regions[i].start;
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hw_mem_regions[i].bus_id = g_mmu_mem_regions[i].bus_id;
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hw_mem_regions[i].caps = g_mmu_mem_regions[i].caps;
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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assert(__builtin_popcount(hw_mem_regions[i].bus_id) == 1);
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#endif
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assert(hw_mem_regions[i].pool_size % MMU_PAGE_SIZE == 0);
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}
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//First reserve memory regions used for irom and drom, as we must follow the way how 1st bootloader load them
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s_reserve_irom_region(hw_mem_regions, SOC_MMU_LINEAR_ADDRESS_REGION_NUM);
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s_reserve_drom_region(hw_mem_regions, SOC_MMU_LINEAR_ADDRESS_REGION_NUM);
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if (SOC_MMU_LINEAR_ADDRESS_REGION_NUM > 1) {
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//Now we can coalesce adjacent regions
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for (int i = 1; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
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mmu_linear_mem_t *a = &hw_mem_regions[i - 1];
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mmu_linear_mem_t *b = &hw_mem_regions[i];
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if ((b->free_head == a->end) && (b->caps == a->caps)) {
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a->caps = MEM_REGION_MERGED;
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b->bus_id |= a->bus_id;
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b->start = a->start;
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b->pool_size += a->pool_size;
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b->free_head = a->free_head;
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b->free_size += a->free_size;
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}
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}
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}
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//Count the mem regions left after coalescing
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uint32_t region_num = 0;
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for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
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if(hw_mem_regions[i].caps != MEM_REGION_MERGED) {
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region_num++;
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}
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}
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ESP_EARLY_LOGV(TAG, "after coalescing, %d regions are left", region_num);
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//Initialise `s_mmu_ctx.mem_regions[]`, as we've done all static allocation, to prepare available virtual memory regions
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uint32_t available_region_idx = 0;
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s_mmu_ctx.num_regions = region_num;
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for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
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if (hw_mem_regions[i].caps == MEM_REGION_MERGED) {
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continue;
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}
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memcpy(&s_mmu_ctx.mem_regions[available_region_idx], &hw_mem_regions[i], sizeof(mmu_linear_mem_t));
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available_region_idx++;
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}
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assert(available_region_idx == region_num);
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}
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esp_err_t esp_mmu_get_largest_free_block(int caps, size_t *out_len)
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{
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ESP_RETURN_ON_FALSE(out_len, ESP_ERR_INVALID_ARG, TAG, "null pointer");
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if (caps & MMU_MEM_CAP_EXEC) {
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if ((caps & MMU_MEM_CAP_8BIT) || (caps & MMU_MEM_CAP_WRITE)) {
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//None of the executable memory are expected to be 8-bit accessible or writable.
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return ESP_ERR_INVALID_ARG;
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}
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}
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*out_len = 0;
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size_t max = 0;
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for (int i = 0; i < s_mmu_ctx.num_regions; i++) {
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if ((s_mmu_ctx.mem_regions[i].caps & caps) == caps) {
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if (s_mmu_ctx.mem_regions[i].free_size > max) {
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max = s_mmu_ctx.mem_regions[i].free_size;
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}
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}
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}
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*out_len = max;
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return ESP_OK;
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}
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esp_err_t esp_mmu_find_vaddr_range(size_t size, uint32_t caps, const void **out_ptr)
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{
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ESP_RETURN_ON_FALSE(out_ptr, ESP_ERR_INVALID_ARG, TAG, "null pointer");
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if (caps & MMU_MEM_CAP_EXEC) {
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if ((caps & MMU_MEM_CAP_8BIT) || (caps & MMU_MEM_CAP_WRITE)) {
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//None of the executable memory are expected to be 8-bit accessible or writable.
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return ESP_ERR_INVALID_ARG;
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}
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caps |= MMU_MEM_CAP_32BIT;
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}
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size_t aligned_size = ALIGN_UP_BY(size, MMU_PAGE_SIZE);
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bool is_match = false;
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uint32_t laddr = 0;
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for (int i = 0; i < s_mmu_ctx.num_regions; i++) {
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if ((s_mmu_ctx.mem_regions[i].caps & caps) == caps) {
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if (s_mmu_ctx.mem_regions[i].free_size < aligned_size) {
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continue;
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} else {
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laddr = (uint32_t)s_mmu_ctx.mem_regions[i].free_head;
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s_mmu_ctx.mem_regions[i].free_head += aligned_size;
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s_mmu_ctx.mem_regions[i].free_size -= aligned_size;
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is_match = true;
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break;
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}
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}
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}
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ESP_RETURN_ON_FALSE(is_match, ESP_ERR_NOT_FOUND, TAG, "no such vaddr range");
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ESP_EARLY_LOGV(TAG, "found laddr is 0x%x", laddr);
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if (caps & MMU_MEM_CAP_EXEC) {
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laddr = mmu_ll_laddr_to_vaddr(laddr, MMU_VADDR_INSTRUCTION);
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} else {
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laddr = mmu_ll_laddr_to_vaddr(laddr, MMU_VADDR_DATA);
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}
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*out_ptr = (void *)laddr;
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return ESP_OK;
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}
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esp_err_t esp_mmu_dump_region_usage(void)
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{
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for (int i = 0; i < s_mmu_ctx.num_regions; i++) {
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ESP_EARLY_LOGI(TAG, "bus_id: 0x%x", s_mmu_ctx.mem_regions[i].bus_id);
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ESP_EARLY_LOGI(TAG, "start: 0x%x", s_mmu_ctx.mem_regions[i].start);
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ESP_EARLY_LOGI(TAG, "end: 0x%x", s_mmu_ctx.mem_regions[i].end);
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ESP_EARLY_LOGI(TAG, "pool_size: 0x%x", s_mmu_ctx.mem_regions[i].pool_size);
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ESP_EARLY_LOGI(TAG, "free_head: 0x%x", s_mmu_ctx.mem_regions[i].free_head);
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ESP_EARLY_LOGI(TAG, "free_size: 0x%x", s_mmu_ctx.mem_regions[i].free_size);
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ESP_EARLY_LOGI(TAG, "caps: 0x%x\n", s_mmu_ctx.mem_regions[i].caps);
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}
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return ESP_OK;
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}
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