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1fc288556c
This is mostly important on ESP32 ECO3 with the ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core before we disable the TG1 WDT then the first CPU can get stuck in WDT ISR handle_livelock_int routine waiting for the other CPU. |
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.. | ||
arch | ||
include | ||
soc | ||
async_memcpy_impl_gdma.c | ||
CMakeLists.txt | ||
cpu_start.c | ||
panic_handler.c |