esp-idf/components/ulp/test_apps/.build-test-rules.yml
Marius Vikhammer 00eb97725b feat(system): support choosing xtal as rtc-fast clock src on P4 and C5
With xtal as rtc-fast clock source the LP-Core can run at twice the default
clock frequency. 40 MHz as opposed to 20 MHz.
2024-09-19 17:30:44 +08:00

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YAML

# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
components/ulp/test_apps/lp_core/lp_core_basic_tests:
disable:
- if: SOC_LP_CORE_SUPPORTED != 1
- if: CONFIG_NAME == "xtal" and SOC_CLK_LP_FAST_SUPPORT_XTAL != 1
components/ulp/test_apps/lp_core/lp_core_hp_uart:
disable:
- if: SOC_LP_CORE_SUPPORTED != 1
components/ulp/test_apps/ulp_fsm:
enable:
- if: SOC_ULP_FSM_SUPPORTED == 1
components/ulp/test_apps/ulp_riscv:
disable:
- if: SOC_RISCV_COPROC_SUPPORTED != 1