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3bfc134a23
This commit adds sliced C2M ops, when the msync is called in task. This way it gives a breath of the critical section, so that a long C2M operation will not disable interrupts for a long time
32 lines
1.5 KiB
Plaintext
32 lines
1.5 KiB
Plaintext
menu "ESP-MM: Memory Management Configurations"
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config ESP_MM_CACHE_MSYNC_C2M_CHUNKED_OPS
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depends on SOC_CACHE_WRITEBACK_SUPPORTED
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bool "Enable esp_cache_msync C2M chunked operation"
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help
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`esp_cache_msync` C2M direction takes critical sections, which means during
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the operation, the interrupts are disabled. Whereas Cache writebacks for
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large buffers could be especially time intensive, and might cause interrupts
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to be disabled for a significant amount of time.
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Sometimes you want other ISRs to be responded during this C2M process.
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This option is to slice one C2M operation into multiple chunks,
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with CONFIG_ESP_MM_CACHE_MSYNC_C2M_CHUNKED_OPS_MAX_LEN max len. This will give you
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a breath during the C2M process as sometimes the C2M process is quite long.
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Note if the buffer processed by the `esp_cache_msync` (C2M sliced) is interrupted by an ISR,
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and this ISR also accesses this buffer, this may lead to data coherence issue.
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config ESP_MM_CACHE_MSYNC_C2M_CHUNKED_OPS_MAX_LEN
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hex "Max len in bytes per C2M chunk"
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depends on ESP_MM_CACHE_MSYNC_C2M_CHUNKED_OPS
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range 0 0x80000
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default 0x20000 if IDF_TARGET_ESP32P4
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default 0x2000 if IDF_TARGET_ESP32S2
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default 0x8000 if IDF_TARGET_ESP32S3
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help
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Max len in bytes per C2M chunk, operations with size over the max len will be
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sliced into multiple chunks.
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endmenu
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