/* * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "ld.common" /* Default entry point */ ENTRY(call_start_cpu0); SECTIONS { /** * RTC fast memory holds RTC wake stub code, * including from any source file named rtc_wake_stub*.c */ .rtc.text : { ALIGNED_SYMBOL(4, _rtc_text_start) mapping[rtc_text] *rtc_wake_stub*.*(.literal .text .literal.* .text.*) _rtc_text_end = ABSOLUTE(.); } > rtc_iram_seg /** * This section is required to skip rtc.text area because rtc_iram_seg and * rtc_data_seg are reflect the same address space on different buses. */ .rtc.dummy : { _rtc_dummy_start = ABSOLUTE(.); _rtc_fast_start = ABSOLUTE(.); . = SIZEOF(.rtc.text); _rtc_dummy_end = ABSOLUTE(.); } > rtc_data_seg /** * This section located in RTC FAST Memory area. * It holds data marked with RTC_FAST_ATTR attribute. * See the file "esp_attr.h" for more information. */ .rtc.force_fast : { ALIGNED_SYMBOL(4, _rtc_force_fast_start) mapping[rtc_force_fast] *(.rtc.force_fast .rtc.force_fast.*) ALIGNED_SYMBOL(4, _rtc_force_fast_end) } > rtc_data_seg /** * RTC data section holds RTC wake stub * data/rodata, including from any source file * named rtc_wake_stub*.c and the data marked with * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. * The memory location of the data is dependent on * CONFIG_ESP32_RTCDATA_IN_FAST_MEM option. */ .rtc.data : { _rtc_data_start = ABSOLUTE(.); mapping[rtc_data] *rtc_wake_stub*.*(.data .rodata .data.* .rodata.*) _rtc_data_end = ABSOLUTE(.); } > rtc_data_location /* RTC bss, from any source file named rtc_wake_stub*.c */ .rtc.bss (NOLOAD) : { _rtc_bss_start = ABSOLUTE(.); *rtc_wake_stub*.*(.bss .bss.*) *rtc_wake_stub*.*(COMMON) mapping[rtc_bss] _rtc_bss_end = ABSOLUTE(.); } > rtc_data_location /** * This section holds data that should not be initialized at power up * and will be retained during deep sleep. * User data marked with RTC_NOINIT_ATTR will be placed * into this section. See the file "esp_attr.h" for more information. * The memory location of the data is dependent on * CONFIG_ESP32_RTCDATA_IN_FAST_MEM option. */ .rtc_noinit (NOLOAD): { ALIGNED_SYMBOL(4, _rtc_noinit_start) *(.rtc_noinit .rtc_noinit.*) ALIGNED_SYMBOL(4, _rtc_noinit_end) } > rtc_data_location /** * This section located in RTC SLOW Memory area. * It holds data marked with RTC_SLOW_ATTR attribute. * See the file "esp_attr.h" for more information. */ .rtc.force_slow : { ALIGNED_SYMBOL(4, _rtc_force_slow_start) *(.rtc.force_slow .rtc.force_slow.*) ALIGNED_SYMBOL(4, _rtc_force_slow_end) } > rtc_slow_seg /** * This section holds RTC FAST data that should have fixed addresses. * The data are not initialized at power-up and are retained during deep * sleep. */ .rtc_fast_reserved (NOLOAD): { ALIGNED_SYMBOL(4, _rtc_fast_reserved_start) /** * New data can only be added here to ensure existing data are not moved. * Because data have adhered to the end of the segment and code is relied * on it. * >> put new data here << */ KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) _rtc_fast_reserved_end = ABSOLUTE(.); } > rtc_fast_reserved_seg _rtc_fast_reserved_length = _rtc_fast_reserved_end - _rtc_fast_reserved_start; ASSERT((_rtc_fast_reserved_length <= LENGTH(rtc_fast_reserved_seg)), "RTC FAST reserved segment data does not fit.") /** * This section holds RTC SLOW data that should have fixed addresses. * The data are not initialized at power-up and are retained during deep * sleep. */ .rtc_slow_reserved (NOLOAD): { ALIGNED_SYMBOL(4, _rtc_slow_reserved_start) /** * New data can only be added here to ensure existing data are not moved. * Because data have adhered to the end of the segment and code is relied * on it. * >> put new data here << */ *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) _rtc_slow_reserved_end = ABSOLUTE(.); } > rtc_slow_reserved_seg _rtc_slow_reserved_length = _rtc_slow_reserved_end - _rtc_slow_reserved_start; _rtc_reserved_length = _rtc_slow_reserved_length; ASSERT((_rtc_slow_reserved_length <= LENGTH(rtc_slow_reserved_seg)), "RTC SLOW reserved segment data does not fit.") /* Get size of rtc slow data based on rtc_data_location alias */ _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) ? (_rtc_force_slow_end - _rtc_data_start) : (_rtc_force_slow_end - _rtc_force_slow_start); _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) ? (_rtc_force_fast_end - _rtc_fast_start) : (_rtc_noinit_end - _rtc_fast_start); ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") /* Send .iram0 code to iram */ .iram0.vectors : { _iram_start = ABSOLUTE(.); /* Vectors go to IRAM */ _vector_table = ABSOLUTE(.); . = 0x0; KEEP(*(.WindowVectors.text)); . = 0x180; KEEP(*(.Level2InterruptVector.text)); . = 0x1c0; KEEP(*(.Level3InterruptVector.text)); . = 0x200; KEEP(*(.Level4InterruptVector.text)); . = 0x240; KEEP(*(.Level5InterruptVector.text)); . = 0x280; KEEP(*(.DebugExceptionVector.text)); . = 0x2c0; KEEP(*(.NMIExceptionVector.text)); . = 0x300; KEEP(*(.KernelExceptionVector.text)); . = 0x340; KEEP(*(.UserExceptionVector.text)); . = 0x3C0; KEEP(*(.DoubleExceptionVector.text)); . = 0x400; _invalid_pc_placeholder = ABSOLUTE(.); *(.*Vector.literal) *(.UserEnter.literal); *(.UserEnter.text); . = ALIGN (16); *(.entry.text) *(.init.literal) *(.init) _init_end = ABSOLUTE(.); } > iram0_0_seg .iram0.text : { /* Code marked as running out of IRAM */ _iram_text_start = ABSOLUTE(.); mapping[iram0_text] } > iram0_0_seg .dram0.data : { _data_start = ABSOLUTE(.); *(.gnu.linkonce.d.*) *(.data1) *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) *(.gnu.linkonce.s2.*) *(.jcr) mapping[dram0_data] _data_end = ABSOLUTE(.); } > dram0_0_seg /** * This section holds data that won't be initialised when startup. * This section locates in External RAM region. */ .ext_ram_noinit (NOLOAD) : { _ext_ram_noinit_start = ABSOLUTE(.); *(.ext_ram_noinit*) ALIGNED_SYMBOL(4, _ext_ram_noinit_end) } > extern_ram_seg /** * This section holds data that should not be initialized at power up. * The section located in Internal SRAM memory region. The macro _NOINIT * can be used as attribute to place data into this section. * See the "esp_attr.h" file for more information. */ .noinit (NOLOAD): { ALIGNED_SYMBOL(4, _noinit_start) *(.noinit .noinit.*) ALIGNED_SYMBOL(4, _noinit_end) } > dram0_0_seg /* External Memory BSS. (Variables with EXT_RAM_BSS_ATTR attribute). */ .ext_ram.bss (NOLOAD) : { ALIGNED_SYMBOL(4, _ext_ram_bss_start) mapping[extern_ram] ALIGNED_SYMBOL(4, _ext_ram_bss_end) } > extern_ram_seg /* Shared RAM */ .dram0.bss (NOLOAD) : { ALIGNED_SYMBOL(8, _bss_start) /** * ldgen places all bss-related data to mapping[dram0_bss] * (See components/esp_system/app.lf). */ mapping[dram0_bss] ALIGNED_SYMBOL(8, _bss_end) } > dram0_0_seg ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") .flash.appdesc : ALIGN(0x10) { /** * Mark flash.rodata start. * This can be used for mmu driver to maintain virtual address */ _rodata_reserved_start = ABSOLUTE(.); _rodata_start = ABSOLUTE(.); /* !DO NOT PUT ANYTHING BEFORE THIS! */ /* Should be the first. App version info. */ *(.rodata_desc .rodata_desc.*) /* Should be the second. Custom app version info. */ *(.rodata_custom_desc .rodata_custom_desc.*) /** * Create an empty gap within this section. Thanks to this, the end of this * section will match .flah.rodata's begin address. Thus, both sections * will be merged when creating the final bin image. */ . = ALIGN(ALIGNOF(.flash.rodata)); } > default_rodata_seg ASSERT_SECTIONS_GAP(.flash.appdesc, .flash.rodata) .flash.rodata : ALIGN(0x10) { _flash_rodata_start = ABSOLUTE(.); mapping[flash_rodata] *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ *(.gnu.linkonce.r.*) *(.rodata1) /* C++ exception handlers table. */ ALIGNED_SYMBOL(4, __XT_EXCEPTION_TABLE_) *(.xt_except_table) *(.gcc_except_table .gcc_except_table.*) *(.gnu.linkonce.e.*) ALIGNED_SYMBOL(4, __XT_EXCEPTION_DESCS_) *(.xt_except_desc) *(.gnu.linkonce.h.*) __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); *(.xt_except_desc_end) #if CONFIG_COMPILER_CXX_EXCEPTIONS ALIGNED_SYMBOL(4, __eh_frame) KEEP(*(.eh_frame)) /** * As we are not linking with crtend.o, which includes the CIE terminator * (see __FRAME_END__ in libgcc sources), it is manually provided here. */ LONG(0); #endif // CONFIG_COMPILER_CXX_EXCEPTIONS /** * C++ constructor tables. * * Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt. */ ALIGNED_SYMBOL(4, __init_array_start) KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*))) __init_array_end = ABSOLUTE(.); /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ ALIGNED_SYMBOL(4, soc_reserved_memory_region_start) KEEP (*(.reserved_memory_address)) soc_reserved_memory_region_end = ABSOLUTE(.); /* System init functions registered via ESP_SYSTEM_INIT_FN */ ALIGNED_SYMBOL(4, _esp_system_init_fn_array_start) KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) _esp_system_init_fn_array_end = ABSOLUTE(.); _rodata_end = ABSOLUTE(.); /* Literals are also RO data. */ _lit4_start = ABSOLUTE(.); *(*.lit4) *(.lit4.*) *(.gnu.linkonce.lit4.*) _lit4_end = ABSOLUTE(.); /* TLS data. */ ALIGNED_SYMBOL(4, _thread_local_start) *(.tdata) *(.tdata.*) *(.tbss) *(.tbss.*) _thread_local_end = ABSOLUTE(.); } > default_rodata_seg _flash_rodata_align = ALIGNOF(.flash.rodata); /** * This section contains all the rodata that is not used * at runtime, helping to avoid an increase in binary size. */ .flash.rodata_noload (NOLOAD) : { /** * This symbol marks the end of flash.rodata. It can be utilized by the MMU * driver to maintain the virtual address. * NOLOAD rodata may not be included in this section. */ _rodata_reserved_end = ABSOLUTE(.); mapping[rodata_noload] } > default_rodata_seg .flash.text : { _stext = .; /** * Mark the start of flash.text. * This can be used by the MMU driver to maintain the virtual address. */ _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); mapping[flash_text] *(.stub) *(.gnu.warning) *(.gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ /** * CPU will try to prefetch up to 16 bytes of of instructions. * This means that any configuration (e.g. MMU, PMS) must allow * safe access to up to 16 bytes after the last real instruction, * add dummy bytes to ensure this. */ . += _esp_flash_mmap_prefetch_pad_size; _text_end = ABSOLUTE(.); /** * Mark the flash.text end. * This can be used for MMU driver to maintain virtual address. */ _instruction_reserved_end = ABSOLUTE(.); _etext = .; /** * Similar to _iram_start, this symbol goes here so it is * resolved by addr2line in preference to the first symbol in * the flash.text segment. */ _flash_cache_start = ABSOLUTE(0); } > default_code_seg /* Marks the end of IRAM code segment */ .iram0.text_end (NOLOAD) : { ALIGNED_SYMBOL(4, _iram_text_end) } > iram0_0_seg .iram0.data : { ALIGNED_SYMBOL(4, _iram_data_start) mapping[iram0_data] _iram_data_end = ABSOLUTE(.); } > iram0_0_seg .iram0.bss (NOLOAD) : { ALIGNED_SYMBOL(4, _iram_bss_start) mapping[iram0_bss] _iram_bss_end = ABSOLUTE(.); ALIGNED_SYMBOL(4, _iram_end) } > iram0_0_seg /* Marks the end of data, bss and possibly rodata */ .dram0.heap_start (NOLOAD) : { /* Lowest possible start address for the heap */ ALIGNED_SYMBOL(8, _heap_low_start) } > dram0_0_seg /** * This section will be used by the debugger and disassembler to get more * information about raw data present in the code. * Indeed, it may be required to add some padding at some points in the code * in order to align a branch/jump destination on a particular bound. * Padding these instructions will generate null bytes that shall be * interpreted as data, and not code by the debugger or disassembler. * This section will only be present in the ELF file, not in the final binary * For more details, check GCC-212 */ .xt.prop 0 : { KEEP (*(.xt.prop .xt.prop.* .gnu.linkonce.prop.*)) } .xt.lit 0 : { KEEP (*(.xt.lit .xt.lit.* .gnu.linkonce.p.*)) } /DISCARD/ : { *(.eh_frame_hdr) #if !CONFIG_COMPILER_CXX_EXCEPTIONS *(.eh_frame) #endif // !CONFIG_COMPILER_CXX_EXCEPTIONS } } ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), "IRAM0 segment data does not fit.") ASSERT(((_heap_low_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")