/* Tests for the spi_master device driver */ #include #include #include #include #include #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" #include "freertos/queue.h" #include "freertos/xtensa_api.h" #include "unity.h" #include "driver/spi_master.h" #include "driver/spi_slave.h" #include "esp_heap_caps.h" #include "esp_log.h" #include "soc/spi_periph.h" #include "test_utils.h" #include "test/test_common_spi.h" #include "soc/gpio_periph.h" #include "sdkconfig.h" #include "../cache_utils.h" #include "soc/soc_memory_layout.h" #include "driver/spi_common_internal.h" const static char TAG[] = "test_spi"; static void check_spi_pre_n_for(int clk, int pre, int n) { esp_err_t ret; spi_device_handle_t handle; spi_device_interface_config_t devcfg={ .command_bits=0, .address_bits=0, .dummy_bits=0, .clock_speed_hz=clk, .duty_cycle_pos=128, .mode=0, .spics_io_num=21, .queue_size=3 }; char sendbuf[16]=""; spi_transaction_t t; memset(&t, 0, sizeof(t)); ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle); TEST_ASSERT(ret==ESP_OK); t.length=16*8; t.tx_buffer=sendbuf; ret=spi_device_transmit(handle, &t); spi_dev_t* hw = spi_periph_signal[TEST_SPI_HOST].hw; printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, hw->clock.clkdiv_pre+1, hw->clock.clkcnt_n+1); TEST_ASSERT(hw->clock.clkcnt_n+1==n); TEST_ASSERT(hw->clock.clkdiv_pre+1==pre); ret=spi_bus_remove_device(handle); TEST_ASSERT(ret==ESP_OK); } TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") { spi_bus_config_t buscfg={ .mosi_io_num=PIN_NUM_MOSI, .miso_io_num=PIN_NUM_MISO, .sclk_io_num=PIN_NUM_CLK, .quadwp_io_num=-1, .quadhd_io_num=-1 }; esp_err_t ret; ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); TEST_ASSERT(ret==ESP_OK); check_spi_pre_n_for(26000000, 1, 3); check_spi_pre_n_for(20000000, 1, 4); check_spi_pre_n_for(8000000, 1, 10); check_spi_pre_n_for(800000, 2, 50); check_spi_pre_n_for(100000, 16, 50); check_spi_pre_n_for(333333, 4, 60); check_spi_pre_n_for(900000, 2, 44); check_spi_pre_n_for(1, 8192, 64); //Actually should generate the minimum clock speed, 152Hz check_spi_pre_n_for(26000000, 1, 3); ret=spi_bus_free(TEST_SPI_HOST); TEST_ASSERT(ret==ESP_OK); } static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) { spi_bus_config_t buscfg={ .mosi_io_num=PIN_NUM_MOSI, .miso_io_num=PIN_NUM_MOSI, .sclk_io_num=PIN_NUM_CLK, .quadwp_io_num=-1, .quadhd_io_num=-1, .max_transfer_sz=4096*3 }; spi_device_interface_config_t devcfg={ .command_bits=0, .address_bits=0, .dummy_bits=0, .clock_speed_hz=clkspeed, .duty_cycle_pos=128, .mode=0, .spics_io_num=PIN_NUM_CS, .queue_size=3, }; esp_err_t ret; spi_device_handle_t handle; ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma?1:0); TEST_ASSERT(ret==ESP_OK); ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle); TEST_ASSERT(ret==ESP_OK); //connect MOSI to two devices breaks the output, fix it. spitest_gpio_output_sel(PIN_NUM_MOSI, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); printf("Bus/dev inited.\n"); return handle; } static int spi_test(spi_device_handle_t handle, int num_bytes) { esp_err_t ret; int x; bool success = true; srand(num_bytes); char *sendbuf=heap_caps_malloc((num_bytes+3)&(~3), MALLOC_CAP_DMA); char *recvbuf=heap_caps_malloc((num_bytes+3)&(~3), MALLOC_CAP_DMA); for (x=0; x> 1; if (in&0x80) out |= 0x80; in = in << 1; } return out; } void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) { spi_device_handle_t spi; ESP_LOGI(MASTER_TAG, ">>>>>>>>> TEST %s FIRST <<<<<<<<<<<", lsb_first?"LSB":"MSB"); //initial master, mode 0, 1MHz spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); buscfg.quadhd_io_num = UNCONNECTED_PIN; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.clock_speed_hz = 1*1000*1000; if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST; TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); //connecting pins to two peripherals breaks the output, fix it. spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out); spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]); spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out); for (int i= 0; i < 8; i++) { //prepare slave tx data slave_txdata_t slave_txdata = (slave_txdata_t) { .start = spitest_slave_send + 4*(i%3), .len = 256, }; xQueueSend(slave_context->data_to_send, &slave_txdata, portMAX_DELAY); vTaskDelay(50); //prepare master tx data int cmd_bits = (i+1)*2; int addr_bits = 56-8*i; int round_up = (cmd_bits+addr_bits+7)/8*8; addr_bits = round_up - cmd_bits; spi_transaction_ext_t trans = (spi_transaction_ext_t) { .base = { .flags = SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR, .addr = 0x456789abcdef0123, .cmd = 0x9876, }, .command_bits = cmd_bits, .address_bits = addr_bits, }; ESP_LOGI( MASTER_TAG, "===== test%d =====", i ); ESP_LOGI(MASTER_TAG, "cmd_bits： %d, addr_bits: %d", cmd_bits, addr_bits); TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t*)&trans)); //wait for both master and slave end size_t rcv_len; slave_rxdata_t *rcv_data = xRingbufferReceive(slave_context->data_received, &rcv_len, portMAX_DELAY); rcv_len-=8; uint8_t *buffer = rcv_data->data; ESP_LOGI(SLAVE_TAG, "trans_len: %d", rcv_len); TEST_ASSERT_EQUAL(rcv_len, (rcv_data->len+7)/8); TEST_ASSERT_EQUAL(rcv_data->len, cmd_bits+addr_bits); ESP_LOG_BUFFER_HEX("slave rx", buffer, rcv_len); uint16_t cmd_expected = trans.base.cmd & (BIT(cmd_bits) - 1); uint64_t addr_expected = trans.base.addr & ((1ULL<> (16-cmd_bits); int remain_bits = cmd_bits % 8; uint64_t addr_got = *(uint64_t*)data_ptr; data_ptr += 8; addr_got = __builtin_bswap64(addr_got); addr_got = (addr_got << remain_bits); addr_got |= (*data_ptr >> (8-remain_bits)); addr_got = addr_got >> (64-addr_bits); if (lsb_first) { cmd_got = __builtin_bswap16(cmd_got); addr_got = __builtin_bswap64(addr_got); uint8_t *swap_ptr = (uint8_t*)&cmd_got; swap_ptr[0] = bitswap(swap_ptr[0]); swap_ptr[1] = bitswap(swap_ptr[1]); cmd_got = cmd_got >> (16-cmd_bits); swap_ptr = (uint8_t*)&addr_got; for (int j = 0; j < 8; j++) swap_ptr[j] = bitswap(swap_ptr[j]); addr_got = addr_got >> (64-addr_bits); } ESP_LOGI(SLAVE_TAG, "cmd_got: %04X, addr_got: %08X%08X", cmd_got, (uint32_t)(addr_got>>32), (uint32_t)addr_got); TEST_ASSERT_EQUAL_HEX16(cmd_expected, cmd_got); if (addr_bits > 0) { TEST_ASSERT_EQUAL_HEX32(addr_expected, addr_got); TEST_ASSERT_EQUAL_HEX32(addr_expected >> 8, addr_got >> 8); } //clean vRingbufferReturnItem(slave_context->data_received, buffer); } TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK); } TEST_CASE("SPI master variable cmd & addr test","[spi]") { spi_slave_task_context_t slave_context = {}; esp_err_t err = init_slave_context( &slave_context ); TEST_ASSERT( err == ESP_OK ); TaskHandle_t handle_slave; xTaskCreate( spitest_slave_task, "spi_slave", 4096, &slave_context, 0, &handle_slave); //initial slave, mode 0, no dma int dma_chan = 0; int slave_mode = 0; spi_bus_config_t slv_buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); spi_slave_interface_config_t slvcfg=SPI_SLAVE_TEST_DEFAULT_CONFIG(); slvcfg.mode = slave_mode; //Initialize SPI slave interface TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, dma_chan) ); test_cmd_addr(&slave_context, false); test_cmd_addr(&slave_context, true); vTaskDelete( handle_slave ); handle_slave = 0; deinit_slave_context(&slave_context); TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK); ESP_LOGI(MASTER_TAG, "test passed."); } void test_dummy(spi_device_handle_t spi, int dummy_n, uint8_t* data_to_send, int len) { ESP_LOGI(TAG, "testing dummy n=%d", dummy_n); WORD_ALIGNED_ATTR uint8_t slave_buffer[len+(dummy_n+7)/8]; spi_slave_transaction_t slave_t = { .tx_buffer = slave_buffer, .rx_buffer = slave_buffer, .length = len*8+((dummy_n+7)&(~8))+32, //receive more bytes to avoid slave discarding data }; TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY)); vTaskDelay(50); spi_transaction_ext_t t = { .base = { .tx_buffer = data_to_send, .length = (len+1)*8, //send one more byte force slave receive all data .flags = SPI_TRANS_VARIABLE_DUMMY, }, .dummy_bits = dummy_n, }; TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t*)&t)); spi_slave_transaction_t *ret_slave; TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_slave, portMAX_DELAY)); TEST_ASSERT(ret_slave == &slave_t); ESP_LOG_BUFFER_HEXDUMP("rcv", slave_buffer, len+4, ESP_LOG_INFO); int skip_cnt = dummy_n/8; int dummy_remain = dummy_n % 8; uint8_t *slave_ptr = slave_buffer; if (dummy_remain > 0) { for (int i = 0; i < len; i++) { slave_ptr[0] = (slave_ptr[skip_cnt] << dummy_remain) | (slave_ptr[skip_cnt+1] >> (8-dummy_remain)); slave_ptr++; } } else { for (int i = 0; i < len; i++) { slave_ptr[0] = slave_ptr[skip_cnt]; slave_ptr++; } } TEST_ASSERT_EQUAL_HEX8_ARRAY(data_to_send, slave_buffer, len); } TEST_CASE("SPI master variable dummy test", "[spi]") { spi_device_handle_t spi; spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); dev_cfg.flags = SPI_DEVICE_HALFDUPLEX; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi)); spi_slave_interface_config_t slave_cfg =SPI_SLAVE_TEST_DEFAULT_CONFIG(); TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slave_cfg, 0)); spitest_gpio_output_sel(bus_cfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); spitest_gpio_output_sel(bus_cfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out); spitest_gpio_output_sel(dev_cfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]); spitest_gpio_output_sel(bus_cfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out); uint8_t data_to_send[] = {0x12, 0x34, 0x56, 0x78}; test_dummy(spi, 0, data_to_send, sizeof(data_to_send)); test_dummy(spi, 1, data_to_send, sizeof(data_to_send)); test_dummy(spi, 2, data_to_send, sizeof(data_to_send)); test_dummy(spi, 3, data_to_send, sizeof(data_to_send)); test_dummy(spi, 4, data_to_send, sizeof(data_to_send)); test_dummy(spi, 8, data_to_send, sizeof(data_to_send)); test_dummy(spi, 12, data_to_send, sizeof(data_to_send)); test_dummy(spi, 16, data_to_send, sizeof(data_to_send)); spi_slave_free(TEST_SLAVE_HOST); master_free_device_bus(spi); } /******************************************************************************** * Test SPI transaction interval ********************************************************************************/ //Disabled since the check in portENTER_CRITICAL in esp_intr_enable/disable increase the delay #ifndef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE #define RECORD_TIME_PREPARE() uint32_t __t1, __t2 #define RECORD_TIME_START() do {__t1 = xthal_get_ccount();}while(0) #define RECORD_TIME_END(p_time) do{__t2 = xthal_get_ccount(); *p_time = (__t2-__t1);}while(0) #ifdef CONFIG_IDF_TARGET_ESP32 #define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) #elif CONFIG_IDF_TARGET_ESP32S2BETA #define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ) #endif static void speed_setup(spi_device_handle_t* spi, bool use_dma) { esp_err_t ret; spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.queue_size=8; //We want to be able to queue 7 transactions at a time //Initialize the SPI bus and the device to test ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma? GET_DMA_CHAN(TEST_SPI_HOST): 0)); TEST_ASSERT(ret==ESP_OK); ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi); TEST_ASSERT(ret==ESP_OK); } static void sorted_array_insert(uint32_t* array, int* size, uint32_t item) { int pos; for (pos = *size; pos>0; pos--) { if (array[pos-1] < item) break; array[pos] = array[pos-1]; } array[pos]=item; (*size)++; } #define TEST_TIMES 11 static IRAM_ATTR void spi_transmit_measure(spi_device_handle_t spi, spi_transaction_t* trans, uint32_t* t_flight) { RECORD_TIME_PREPARE(); spi_device_transmit(spi, trans); // prime the flash cache RECORD_TIME_START(); spi_device_transmit(spi, trans); RECORD_TIME_END(t_flight); } static IRAM_ATTR void spi_transmit_polling_measure(spi_device_handle_t spi, spi_transaction_t* trans, uint32_t* t_flight) { spi_flash_disable_interrupts_caches_and_other_cpu(); //this can test the code are all in the IRAM at the same time RECORD_TIME_PREPARE(); spi_device_polling_transmit(spi, trans); // prime the flash cache RECORD_TIME_START(); spi_device_polling_transmit(spi, trans); RECORD_TIME_END(t_flight); spi_flash_enable_interrupts_caches_and_other_cpu(); } TEST_CASE("spi_speed","[spi]") { uint32_t t_flight; //to get rid of the influence of randomly interrupts, we measured the performance by median value uint32_t t_flight_sorted[TEST_TIMES]; esp_err_t ret; int t_flight_num = 0; spi_device_handle_t spi; const bool use_dma = true; WORD_ALIGNED_ATTR spi_transaction_t trans = { .length = 1*8, .flags = SPI_TRANS_USE_TXDATA, }; //first work with DMA speed_setup(&spi, use_dma); //record flight time by isr, with DMA t_flight_num = 0; for (int i = 0; i < TEST_TIMES; i++) { spi_transmit_measure(spi, &trans, &t_flight); sorted_array_insert(t_flight_sorted, &t_flight_num, t_flight); } for (int i = 0; i < TEST_TIMES; i++) { ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM_SUPPORT TEST_TARGET_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2])); #endif //acquire the bus to send polling transactions faster ret = spi_device_acquire_bus(spi, portMAX_DELAY); TEST_ESP_OK(ret); //record flight time by polling and with DMA t_flight_num = 0; for (int i = 0; i < TEST_TIMES; i++) { spi_transmit_polling_measure(spi, &trans, &t_flight); sorted_array_insert(t_flight_sorted, &t_flight_num, t_flight); } for (int i = 0; i < TEST_TIMES; i++) { ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM_SUPPORT TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2])); #endif //release the bus spi_device_release_bus(spi); master_free_device_bus(spi); speed_setup(&spi, !use_dma); //record flight time by isr, without DMA t_flight_num = 0; for (int i = 0; i < TEST_TIMES; i++) { spi_transmit_measure(spi, &trans, &t_flight); sorted_array_insert(t_flight_sorted, &t_flight_num, t_flight); } for (int i = 0; i < TEST_TIMES; i++) { ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM_SUPPORT TEST_TARGET_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2])); #endif //acquire the bus to send polling transactions faster ret = spi_device_acquire_bus(spi, portMAX_DELAY); TEST_ESP_OK(ret); //record flight time by polling, without DMA t_flight_num = 0; for (int i = 0; i < TEST_TIMES; i++) { spi_transmit_polling_measure(spi, &trans, &t_flight); sorted_array_insert(t_flight_sorted, &t_flight_num, t_flight); } for (int i = 0; i < TEST_TIMES; i++) { ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i])); } #ifndef CONFIG_SPIRAM_SUPPORT TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2])); #endif //release the bus spi_device_release_bus(spi); master_free_device_bus(spi); } #endif typedef struct { spi_device_handle_t handle; bool finished; } task_context_t; void spi_task1(void* arg) { //task1 send 50 polling transactions, acquire the bus and send another 50 int count=0; spi_transaction_t t = { .flags = SPI_TRANS_USE_TXDATA, .tx_data = { 0x80, 0x12, 0x34, 0x56 }, .length = 4*8, }; spi_device_handle_t handle = ((task_context_t*)arg)->handle; for( int j = 0; j < 50; j ++ ) { TEST_ESP_OK(spi_device_polling_transmit( handle, &t )); ESP_LOGI( TAG, "task1:%d", count++ ); } TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY )); for( int j = 0; j < 50; j ++ ) { TEST_ESP_OK(spi_device_polling_transmit( handle, &t )); ESP_LOGI( TAG, "task1:%d", count++ ); } spi_device_release_bus(handle); ESP_LOGI(TAG, "task1 terminates"); ((task_context_t*)arg)->finished = true; vTaskDelete(NULL); } void spi_task2(void* arg) { int count=0; //task2 acquire the bus, send 50 polling transactions and then 50 non-polling spi_transaction_t t = { .flags = SPI_TRANS_USE_TXDATA, .tx_data = { 0x80, 0x12, 0x34, 0x56 }, .length = 4*8, }; spi_transaction_t *ret_t; spi_device_handle_t handle = ((task_context_t*)arg)->handle; TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY )); for (int i = 0; i < 50; i ++) { TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); ESP_LOGI( TAG, "task2: %d", count++ ); } for( int j = 0; j < 50; j ++ ) { TEST_ESP_OK(spi_device_queue_trans( handle, &t, portMAX_DELAY )); } for( int j = 0; j < 50; j ++ ) { TEST_ESP_OK(spi_device_get_trans_result(handle, &ret_t, portMAX_DELAY)); assert(ret_t == &t); ESP_LOGI( TAG, "task2: %d", count++ ); } spi_device_release_bus(handle); vTaskDelay(1); ESP_LOGI(TAG, "task2 terminates"); ((task_context_t*)arg)->finished = true; vTaskDelete(NULL); } void spi_task3(void* arg) { //task3 send 30 polling transactions, acquire the bus, send 20 polling transactions and then 50 non-polling int count=0; spi_transaction_t t = { .flags = SPI_TRANS_USE_TXDATA, .tx_data = { 0x80, 0x12, 0x34, 0x56 }, .length = 4*8, }; spi_transaction_t *ret_t; spi_device_handle_t handle = ((task_context_t*)arg)->handle; for (int i = 0; i < 30; i ++) { TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); ESP_LOGI( TAG, "task3: %d", count++ ); } TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY )); for (int i = 0; i < 20; i ++) { TEST_ESP_OK(spi_device_polling_transmit(handle, &t)); ESP_LOGI( TAG, "task3: %d", count++ ); } for (int j = 0; j < 50; j++) { TEST_ESP_OK(spi_device_queue_trans(handle, &t, portMAX_DELAY)); } for (int j = 0; j < 50; j++) { TEST_ESP_OK(spi_device_get_trans_result(handle, &ret_t, portMAX_DELAY)); assert(ret_t == &t); ESP_LOGI(TAG, "task3: %d", count++); } spi_device_release_bus(handle); ESP_LOGI(TAG, "task3 terminates"); ((task_context_t*)arg)->finished = true; vTaskDelete(NULL); } TEST_CASE("spi poll tasks","[spi]") { task_context_t context1={}; task_context_t context2={}; task_context_t context3={}; TaskHandle_t task1, task2, task3; esp_err_t ret; spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.queue_size = 100; //Initialize the SPI bus and 3 devices ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); TEST_ASSERT(ret==ESP_OK); ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context1.handle); TEST_ASSERT(ret==ESP_OK); ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context2.handle); TEST_ASSERT(ret==ESP_OK); ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context3.handle); TEST_ASSERT(ret==ESP_OK); xTaskCreate( spi_task1, "task1", 2048, &context1, 0, &task1 ); xTaskCreate( spi_task2, "task2", 2048, &context2, 0, &task2 ); xTaskCreate( spi_task3, "task3", 2048, &context3, 0, &task3 ); for(;;){ vTaskDelay(10); if (context1.finished && context2.finished && context3.finished) break; } TEST_ESP_OK( spi_bus_remove_device(context1.handle) ); TEST_ESP_OK( spi_bus_remove_device(context2.handle) ); TEST_ESP_OK( spi_bus_remove_device(context3.handle) ); TEST_ESP_OK( spi_bus_free(TEST_SPI_HOST) ); } //TODO: add a case when a non-polling transaction happened in the bus-acquiring time and then release the bus then queue a new trans