menu "ESP System Settings" choice ESP_SYSTEM_PANIC prompt "Panic handler behaviour" default ESP_SYSTEM_PANIC_PRINT_REBOOT help If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is invoked. Configure the panic handler's action here. config ESP_SYSTEM_PANIC_PRINT_HALT bool "Print registers and halt" help Outputs the relevant registers over the serial port and halt the processor. Needs a manual reset to restart. config ESP_SYSTEM_PANIC_PRINT_REBOOT bool "Print registers and reboot" help Outputs the relevant registers over the serial port and immediately reset the processor. config ESP_SYSTEM_PANIC_SILENT_REBOOT bool "Silent reboot" help Just resets the processor without outputting anything config ESP_SYSTEM_PANIC_GDBSTUB bool "Invoke GDBStub" select ESP_GDBSTUB_ENABLED help Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem of the crash. endchoice config ESP_SYSTEM_SINGLE_CORE_MODE bool default n help Only initialize and use the main core. config ESP_SYSTEM_RTC_EXT_XTAL # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option # e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on bool default n config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES int "Bootstrap cycles for external 32kHz crystal" depends on ESP_SYSTEM_RTC_EXT_XTAL default 5 if IDF_TARGET_ESP32 default 0 range 0 32768 help To reduce the startup time of an external RTC crystal, we bootstrap it with a 32kHz square wave for a fixed number of cycles. Setting 0 will disable bootstrapping (if disabled, the crystal may take longer to start up or fail to oscillate under some conditions). If this value is too high, a faulty crystal may initially start and then fail. If this value is too low, an otherwise good crystal may not start. To accurately determine if the crystal has started, set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK bool default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE default y if IDF_TARGET_ESP32S2 default y if IDF_TARGET_ESP32C3 default y if IDF_TARGET_ESP32S3 config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP bool "Enable RTC fast memory for dynamic allocations" default y if IDF_TARGET_ESP32 default y if IDF_TARGET_ESP32S2 default y if IDF_TARGET_ESP32C3 default n if IDF_TARGET_ESP32S3 # TODO depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK help This config option allows to add RTC fast memory region to system heap with capability similar to that of DRAM region but without DMA. This memory will be consumed first per heap initialization order by early startup services and scheduler related code. Speed wise RTC fast memory operates on APB clock and hence does not have much performance impact. config ESP_SYSTEM_PD_FLASH bool "PD flash at light sleep when there is no SPIRAM" depends on !SPIRAM default y help If enabled, chip will try to power down flash at light sleep, which costs more time when chip wakes up. Can only be enabled if there is no SPIRAM configured. This option will in fact consider VDD_SDIO auto power value (ESP_PD_OPTION_AUTO) as OFF. Also, it is possible to force a power domain to stay ON during light sleep by using esp_sleep_pd_config() function. config ESP_SYSTEM_PM_POWER_DOWN_CPU bool "Power down CPU in light sleep" depends on IDF_TARGET_ESP32C3 default y help If enabled, the CPU will be powered down in light sleep. Enabling this option will consume 1.68 KB of internal RAM and will reduce sleep current consumption by about 100 uA. menu "Memory protection" config ESP_SYSTEM_MEMPROT_FEATURE bool "Enable memory protection" depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S2 default "y" help If enabled, the permission control module watches all the memory access and fires the panic handler if a permission violation is detected. This feature automatically splits the SRAM memory into data and instruction segments and sets Read/Execute permissions for the instruction part (below given splitting address) and Read/Write permissions for the data part (above the splitting address). The memory protection is effective on all access through the IRAM0 and DRAM0 buses. config ESP_SYSTEM_MEMPROT_FEATURE_LOCK depends on ESP_SYSTEM_MEMPROT_FEATURE bool "Lock memory protection settings" default "y" help Once locked, memory protection settings cannot be changed anymore. The lock is reset only on the chip startup. endmenu # Memory protection config ESP_SYSTEM_EVENT_QUEUE_SIZE int "System event queue size" default 32 help Config system event queue size in different application. config ESP_SYSTEM_EVENT_TASK_STACK_SIZE int "Event loop task stack size" default 2304 help Config system event task stack size in different application. config ESP_MAIN_TASK_STACK_SIZE int "Main task stack size" default 3584 help Configure the "main task" stack size. This is the stack of the task which calls app_main(). If app_main() returns then this task is deleted and its stack memory is freed. choice ESP_MAIN_TASK_AFFINITY prompt "Main task core affinity" default ESP_MAIN_TASK_AFFINITY_CPU0 help Configure the "main task" core affinity. This is the used core of the task which calls app_main(). If app_main() returns then this task is deleted. config ESP_MAIN_TASK_AFFINITY_CPU0 bool "CPU0" config ESP_MAIN_TASK_AFFINITY_CPU1 bool "CPU1" depends on !FREERTOS_UNICORE config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY bool "No affinity" endchoice config ESP_MAIN_TASK_AFFINITY hex default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0 default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1 default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY config ESP_MINIMAL_SHARED_STACK_SIZE int "Minimal allowed size for shared stack" default 2048 help Minimal value of size, in bytes, accepted to execute a expression with shared stack. choice ESP_CONSOLE_UART prompt "Channel for console output" default ESP_CONSOLE_UART_DEFAULT help Select where to send console output (through stdout and stderr). - Default is to use UART0 on pre-defined GPIOs. - If "Custom" is selected, UART0 or UART1 can be chosen, and any pins can be selected. - If "None" is selected, there will be no console output on any UART, except for initial output from ROM bootloader. This ROM output can be suppressed by GPIO strapping or EFUSE, refer to chip datasheet for details. - On chips with USB peripheral, "USB CDC" option redirects output to the CDC port. This option uses the CDC driver in the chip ROM. This option is incompatible with TinyUSB stack. config ESP_CONSOLE_UART_DEFAULT bool "Default: UART0" config ESP_CONSOLE_USB_CDC bool "USB CDC" # The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general. # && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB. depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !USB_ENABLED config ESP_CONSOLE_UART_CUSTOM bool "Custom UART" config ESP_CONSOLE_NONE bool "None" endchoice # Internal option, indicates that console UART is used (and not USB, for example) config ESP_CONSOLE_UART bool default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM config ESP_CONSOLE_MULTIPLE_UART bool default y if !IDF_TARGET_ESP32C3 choice ESP_CONSOLE_UART_NUM prompt "UART peripheral to use for console output (0-1)" depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART default ESP_CONSOLE_UART_CUSTOM_NUM_0 help This UART peripheral is used for console output from the ESP-IDF Bootloader and the app. If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. Due to an ESP32 ROM bug, UART2 is not supported for console output via esp_rom_printf. config ESP_CONSOLE_UART_CUSTOM_NUM_0 bool "UART0" config ESP_CONSOLE_UART_CUSTOM_NUM_1 bool "UART1" endchoice config ESP_CONSOLE_UART_NUM int default 0 if ESP_CONSOLE_UART_DEFAULT default 0 if !ESP_CONSOLE_MULTIPLE_UART default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0 default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1 default -1 if !ESP_CONSOLE_UART config ESP_CONSOLE_UART_TX_GPIO int "UART TX on GPIO#" depends on ESP_CONSOLE_UART_CUSTOM range 0 46 default 1 if IDF_TARGET_ESP32 default 21 if IDF_TARGET_ESP32C3 default 43 help This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including boot log output and default standard output and standard error of the app). If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. config ESP_CONSOLE_UART_RX_GPIO int "UART RX on GPIO#" depends on ESP_CONSOLE_UART_CUSTOM range 0 46 default 3 if IDF_TARGET_ESP32 default 20 if IDF_TARGET_ESP32C3 default 44 help This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including default default standard input of the app). Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART. If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. config ESP_CONSOLE_UART_BAUDRATE int prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM depends on ESP_CONSOLE_UART default 115200 range 1200 4000000 if !PM_ENABLE range 1200 1000000 if PM_ENABLE help This baud rate is used by both the ESP-IDF Bootloader and the app (including boot log output and default standard input/output/error of the app). The app's maximum baud rate depends on the UART clock source. If Power Management is disabled, the UART clock source is the APB clock and all baud rates in the available range will be sufficiently accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be accurate. If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE int "Size of USB CDC RX buffer" depends on ESP_CONSOLE_USB_CDC default 64 range 4 16384 help Set the size of USB CDC RX buffer. Increase the buffer size if your application is often receiving data over USB CDC. config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC" depends on ESP_CONSOLE_USB_CDC default n help If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC. Disabling this option saves about 1kB or RAM. config ESP_INT_WDT bool "Interrupt watchdog" default y help This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time, either because a task turned off interrupts and did not turn them on for a long time, or because an interrupt handler did not return. It will try to invoke the panic handler first and failing that reset the SoC. config ESP_INT_WDT_TIMEOUT_MS int "Interrupt watchdog timeout (ms)" depends on ESP_INT_WDT default 300 if !ESP32_SPIRAM_SUPPORT default 800 if ESP32_SPIRAM_SUPPORT range 10 10000 help The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate. config ESP_INT_WDT_CHECK_CPU1 bool "Also watch CPU1 tick interrupt" depends on ESP_INT_WDT && !FREERTOS_UNICORE default y help Also detect if interrupts on CPU 1 are disabled for too long. config ESP_TASK_WDT bool "Initialize Task Watchdog Timer on startup" default y help The Task Watchdog Timer can be used to make sure individual tasks are still running. Enabling this option will cause the Task Watchdog Timer to be initialized automatically at startup. The Task Watchdog timer can be initialized after startup as well (see Task Watchdog Timer API Reference) config ESP_TASK_WDT_PANIC bool "Invoke panic handler on Task Watchdog timeout" depends on ESP_TASK_WDT default n help If this option is enabled, the Task Watchdog Timer will be configured to trigger the panic handler when it times out. This can also be configured at run time (see Task Watchdog Timer API Reference) config ESP_TASK_WDT_TIMEOUT_S int "Task Watchdog timeout period (seconds)" depends on ESP_TASK_WDT range 1 60 default 5 help Timeout period configuration for the Task Watchdog Timer in seconds. This is also configurable at run time (see Task Watchdog Timer API Reference) config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 bool "Watch CPU0 Idle Task" depends on ESP_TASK_WDT default y help If this option is enabled, the Task Watchdog Timer will watch the CPU0 Idle Task. Having the Task Watchdog watch the Idle Task allows for detection of CPU starvation as the Idle Task not being called is usually a symptom of CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household tasks depend on the Idle Task getting some runtime every now and then. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 bool "Watch CPU1 Idle Task" depends on ESP_TASK_WDT && !FREERTOS_UNICORE default y help If this option is enabled, the Task Wtachdog Timer will wach the CPU1 Idle Task. config ESP_IPC_TASK_STACK_SIZE int "Inter-Processor Call (IPC) task stack size" range 512 65536 if !APPTRACE_ENABLE range 2048 65536 if APPTRACE_ENABLE default 2048 if APPTRACE_ENABLE default 1024 help Configure the IPC tasks stack size. One IPC task runs on each core (in dual core mode), and allows for cross-core function calls. See IPC documentation for more details. The default stack size should be enough for most common use cases. It can be shrunk if you are sure that you do not use any custom IPC functionality. config ESP_IPC_USES_CALLERS_PRIORITY bool "IPC runs at caller's priority" default y depends on !FREERTOS_UNICORE help If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0, and hence IPC task will run at (configMAX_PRIORITIES - 1) priority. config ESP_PANIC_HANDLER_IRAM bool "Place panic handler code in IRAM" default n help If this option is disabled (default), the panic handler code is placed in flash not IRAM. This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor risk, if the flash cache status is also corrupted during the crash. If this option is enabled, the panic handler code is placed in IRAM. This allows the panic handler to run without needing to re-enable cache first. This may be necessary to debug some complex issues with crashes while flash cache is disabled (for example, when writing to SPI flash.) config ESP_DEBUG_STUBS_ENABLE bool default COMPILER_OPTIMIZATION_LEVEL_DEBUG depends on !ESP32_TRAX && !ESP32S2_TRAX help Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging stuff, e.g. GCOV data dump. endmenu # ESP System Settings