/* * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ /* * Soc capabilities file, describing the following chip attributes: * - Peripheral or feature supported or not * - Number of resources (peripheral, channel, etc.) * - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency * supported, etc. * * For boolean definitions: * - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`. * (`#define` blank string causes error when checking by `#if x`) * - if false: not define anything at all. * (`#ifdef x` is true even when `#define 0` is defined before.) * * The code depending on this file uses these boolean definitions as `#if x` or `#if !x`. * (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define * x 0`, it's still a risk.) * * ECO & exceptions: * For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by * `#if x` and `#if !x`, making these missing definitions more obvious. * * These defines are parsed and imported as kconfig variables via the script * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` * * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32s2/include/soc/'` * * For more information see `tools/gen_soc_caps_kconfig/README.md` */ #pragma once /*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_ADC_SUPPORTED 1 #define SOC_DAC_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1 #define SOC_CP_DMA_SUPPORTED 1 #define SOC_CPU_CORES_NUM 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_RISCV_COPROC_SUPPORTED 1 #define SOC_USB_OTG_SUPPORTED 1 #define SOC_PCNT_SUPPORTED 1 #define SOC_WIFI_SUPPORTED 1 #define SOC_ULP_SUPPORTED 1 #define SOC_CCOMP_TIMER_SUPPORTED 1 #define SOC_DIG_SIGN_SUPPORTED 1 #define SOC_HMAC_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 #define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 #define SOC_CACHE_SUPPORT_WRAP 1 #define SOC_FLASH_ENCRYPTION_XTS_AES 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_SLOW_MEM_SUPPORTED 1 #define SOC_PSRAM_DMA_CAPABLE 1 #define SOC_XT_WDT_SUPPORTED 1 #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SIGMADELTA_SUPPORTED 1 /*-------------------------- ADC CAPS ----------------------------------------*/ /*!< SAR ADC Module*/ #define SOC_ADC_RTC_CTRL_SUPPORTED 1 #define SOC_ADC_DIG_CTRL_SUPPORTED 1 #define SOC_ADC_ARBITER_SUPPORTED 1 #define SOC_ADC_FILTER_SUPPORTED 1 #define SOC_ADC_MONITOR_SUPPORTED 1 #define SOC_ADC_PERIPH_NUM (2) #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) #define SOC_ADC_MAX_CHANNEL_NUM (10) /*!< Digital */ #define SOC_ADC_DIGI_CONTROLLER_NUM (2) #define SOC_ADC_PATT_LEN_MAX (32) /*!< Two pattern table, each contains 16 items. Each item takes 1 byte */ #define SOC_ADC_DIGI_MAX_BITWIDTH (12) /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 /*!< RTC */ #define SOC_ADC_MAX_BITWIDTH (13) /*!< Calibration */ #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #define SOC_BROWNOUT_RESET_SUPPORTED 1 /*-------------------------- CP-DMA CAPS -------------------------------------*/ #define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ /*-------------------------- CPU CAPS ----------------------------------------*/ #define SOC_CPU_BREAKPOINTS_NUM 2 #define SOC_CPU_WATCHPOINTS_NUM 2 #define SOC_CPU_WATCHPOINT_SIZE 64 // bytes /*-------------------------- DAC CAPS ----------------------------------------*/ #define SOC_DAC_PERIPH_NUM 2 #define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-S2 has 1 GPIO peripheral #define SOC_GPIO_PORT (1U) #define SOC_GPIO_PIN_COUNT (48) // On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. // On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // Force hold is a new function of ESP32-S2 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) // 0~47 except from 22~25, 47 are valid #define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47)) // GPIO 46, 47 are input only #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47)) // Support to configure slept status #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ #define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */ #define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */ #define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */ /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-S2 have 2 I2C. #define SOC_I2C_NUM (2) #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ //ESP32-S2 support hardware FSM reset #define SOC_I2C_SUPPORT_HW_FSM_RST (1) //ESP32-S2 support hardware clear bus #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) #define SOC_I2C_SUPPORT_REF_TICK (1) #define SOC_I2C_SUPPORT_APB (1) /*-------------------------- APLL CAPS ----------------------------------------*/ #define SOC_CLK_APLL_SUPPORTED (1) // apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) #define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz #define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz #define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation #define SOC_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation /*-------------------------- I2S CAPS ----------------------------------------*/ // ESP32-S2 have 1 I2S #define SOC_I2S_NUM (1U) #define SOC_I2S_SUPPORTS_APLL (1) // ESP32-S2 support APLL #define SOC_I2S_SUPPORTS_DMA_EQUAL (1) #define SOC_I2S_LCD_I80_VARIANT (1) /*-------------------------- LCD CAPS ----------------------------------------*/ /* Notes: On esp32-s2, LCD intel 8080 timing is generated by I2S peripheral */ #define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */ #define SOC_LCD_I80_BUSES (1) /*!< Only I2S0 has LCD mode */ #define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */ /*-------------------------- LEDC CAPS ---------------------------------------*/ #define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX (1) #define SOC_LEDC_SUPPORT_REF_TICK (1) #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) #define SOC_LEDC_CHANNEL_NUM (8) #define SOC_LEDC_TIMER_BIT_WIDE_NUM (14) /*-------------------------- MPU CAPS ----------------------------------------*/ //TODO: correct the caller and remove unsupported lines #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 #define SOC_MPU_MIN_REGION_SIZE 0x20000000U #define SOC_MPU_REGIONS_MAX_NUM 8 #define SOC_MPU_REGION_RO_SUPPORTED 0 #define SOC_MPU_REGION_WO_SUPPORTED 0 /*-------------------------- PCNT CAPS ---------------------------------------*/ #define SOC_PCNT_GROUPS (1U) #define SOC_PCNT_UNITS_PER_GROUP (4) #define SOC_PCNT_CHANNELS_PER_UNIT (2) #define SOC_PCNT_THRES_POINT_PER_UNIT (2) /*-------------------------- RMT CAPS ----------------------------------------*/ #define SOC_RMT_GROUPS (1U) /*!< One RMT group */ #define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */ #define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */ #define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */ #define SOC_RMT_MEM_WORDS_PER_CHANNEL (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ #define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ #define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ #define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmiting specified number of cycles in loop mode */ #define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ #define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ #define SOC_RMT_CHANNEL_CLK_INDEPENDENT (1) /*!< Can select different source clock for each channel */ /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 22 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 #define SOC_RTCIO_HOLD_SUPPORTED 1 #define SOC_RTCIO_WAKE_SUPPORTED 1 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/ #define SOC_SIGMADELTA_NUM 1U #define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 3 #define SOC_SPI_DMA_CHAN_NUM 3 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) #define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 #define SOC_SPI_MAX_PRE_DIVIDER 8192 //#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles #define SOC_SPI_SUPPORT_DDRCLK 1 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 #define SOC_SPI_SUPPORT_CD_SIG 1 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 /// The SPI Slave half duplex mode has been updated greatly in ESP32-S2 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 // Peripheral supports DIO, DOUT, QIO, or QOUT // VSPI (SPI3) only support 1-bit mode #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) // Peripheral supports output given level during its "dummy phase" // Only SPI1 supports this feature #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 #define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_SPI_SUPPORT_OCT 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units #define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units #define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part #define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part /*-------------------------- TIMER GROUP CAPS --------------------------------*/ #define SOC_TIMER_GROUPS (2) #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2) #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64) #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) #define SOC_TIMER_GROUP_TOTAL_TIMERS (4) /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ #define SOC_TOUCH_VERSION_2 (1) /*!