/* * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ /* ROM function interface esp32c6.rom.phy.ld for esp32c6 * * * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b * * Compatible with ROM where ECO version equal or greater to 0. * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ /*************************************** Group rom_phy ***************************************/ /* Functions */ phy_param_addr = 0x40001104; phy_get_romfuncs = 0x40001108; chip761_phyrom_version = 0x4000110c; chip761_phyrom_version_num = 0x40001110; get_rc_dout = 0x40001114; rc_cal = 0x40001118; rom_enter_critical_phy = 0x4000111c; rom_exit_critical_phy = 0x40001120; rom_set_chan_cal_interp = 0x40001124; rom_loopback_mode_en = 0x40001128; rom_bb_bss_cbw40 = 0x4000112c; abs_temp = 0x40001130; get_data_sat = 0x40001134; phy_byte_to_word = 0x40001138; set_chan_reg = 0x4000113c; i2c_master_reset = 0x40001140; rom_set_chan_freq_sw_start = 0x40001144; freq_module_resetn = 0x40001148; freq_chan_en_sw = 0x4000114c; write_chan_freq = 0x40001150; get_freq_mem_param = 0x40001154; get_freq_mem_addr = 0x40001158; bt_txpwr_freq = 0x4000115c; wr_rf_freq_mem = 0x40001160; read_rf_freq_mem = 0x40001164; freq_i2c_mem_write = 0x40001168; freq_num_get_data = 0x4000116c; freq_i2c_num_addr = 0x40001170; freq_i2c_write_set = 0x40001174; pll_dac_mem_update = 0x40001178; pll_cap_mem_update = 0x4000117c; get_rf_freq_cap = 0x40001180; get_rf_freq_init = 0x40001184; phy_en_hw_set_freq = 0x40001188; phy_dis_hw_set_freq = 0x4000118c; rom_pwdet_sar2_init = 0x40001190; rom_en_pwdet = 0x40001194; rom_get_sar_sig_ref = 0x40001198; rom_pwdet_tone_start = 0x4000119c; rom_pwdet_wait_idle = 0x400011a0; rom_read_sar_dout = 0x400011a4; get_tone_sar_dout = 0x400011a8; get_fm_sar_dout = 0x400011ac; txtone_linear_pwr = 0x400011b0; linear_to_db = 0x400011b4; get_power_db = 0x400011b8; meas_tone_pwr_db = 0x400011bc; pkdet_vol_start = 0x400011c0; read_sar2_code = 0x400011c4; get_sar2_vol = 0x400011c8; get_pll_vol = 0x400011cc; tx_pwctrl_bg_init = 0x400011d0; phy_pwdet_always_en = 0x400011d4; phy_pwdet_onetime_en = 0x400011d8; esp_tx_state_out_rom = 0x400011dc; ant_dft_cfg_rom = 0x400011e0; ant_wifitx_cfg_rom = 0x400011e4; ant_wifirx_cfg_rom = 0x400011e8; ant_bttx_cfg_rom = 0x400011ec; ant_btrx_cfg_rom = 0x400011f0; phy_chan_dump_cfg_rom = 0x400011f4; phy_enable_low_rate = 0x400011f8; phy_disable_low_rate = 0x400011fc; phy_is_low_rate_enabled = 0x40001200; phy_dig_reg_backup_rom = 0x40001204; phy_chan_filt_set_rom = 0x40001208; phy_rx11blr_cfg = 0x4000120c; set_cca_rom = 0x40001210; set_rx_sense_rom = 0x40001214; rx_gain_force_rom = 0x40001218; rom_rfpll_set_freq = 0x4000121c; mhz2ieee = 0x40001220; chan_to_freq = 0x40001224; restart_cal = 0x40001228; write_rfpll_sdm = 0x4000122c; wait_rfpll_cal_end = 0x40001230; set_rf_freq_offset = 0x40001234; set_rfpll_freq = 0x40001238; set_channel_rfpll_freq = 0x4000123c; rfpll_cap_correct = 0x40001240; rfpll_cap_init_cal = 0x40001244; write_pll_cap = 0x40001248; read_pll_cap = 0x4000124c; chip_v7_set_chan_ana = 0x40001250; freq_set_reg = 0x40001254; gen_rx_gain_table = 0x40001258; bt_txdc_cal = 0x4000125c; bt_txiq_cal = 0x40001260; txiq_cal_init = 0x40001264; txdc_cal_init = 0x40001268; txdc_cal = 0x4000126c; txiq_get_mis_pwr = 0x40001270; txiq_cover = 0x40001274; rfcal_txiq = 0x40001278; get_power_atten = 0x4000127c; pwdet_ref_code = 0x40001280; pwdet_code_cal = 0x40001284; rfcal_txcap = 0x40001288; tx_cap_init = 0x4000128c; rfcal_pwrctrl = 0x40001290; tx_pwctrl_init_cal = 0x40001294; tx_pwctrl_init = 0x40001298; bt_tx_pwctrl_init = 0x4000129c; rom_i2c_enter_critical = 0x400012a0; rom_i2c_exit_critical = 0x400012a4; rom_get_i2c_read_mask = 0x400012a8; rom_get_i2c_mst0_mask = 0x400012ac; rom_get_i2c_hostid = 0x400012b0; rom_chip_i2c_readReg_org = 0x400012b4; rom_chip_i2c_readReg = 0x400012b8; rom_i2c_readReg = 0x400012bc; rom_chip_i2c_writeReg = 0x400012c0; rom_i2c_writeReg = 0x400012c4; rom_i2c_readReg_Mask = 0x400012c8; rom_i2c_writeReg_Mask = 0x400012cc; rom_set_txcap_reg = 0x400012d0; i2c_paral_set_mst0 = 0x400012d4; i2c_paral_set_read = 0x400012d8; i2c_paral_read = 0x400012dc; i2c_paral_write = 0x400012e0; i2c_paral_write_num = 0x400012e4; i2c_paral_write_mask = 0x400012e8; i2c_sar2_init_code = 0x400012ec; rom_pbus_force_mode = 0x400012f0; rom_pbus_rd_addr = 0x400012f4; rom_pbus_rd_shift = 0x400012f8; rom_pbus_force_test = 0x400012fc; rom_pbus_rd = 0x40001300; rom_pbus_set_rxgain = 0x40001304; rom_pbus_xpd_rx_off = 0x40001308; rom_pbus_xpd_rx_on = 0x4000130c; rom_pbus_xpd_tx_off = 0x40001310; rom_pbus_xpd_tx_on = 0x40001314; rom_set_loopback_gain = 0x40001318; rom_txcal_debuge_mode = 0x4000131c; pbus_debugmode = 0x40001320; pbus_workmode = 0x40001324; pbus_set_dco = 0x40001328; txcal_work_mode = 0x4000132c; rom_start_tx_tone_step = 0x40001330; rom_stop_tx_tone = 0x40001334; disable_agc = 0x40001338; enable_agc = 0x4000133c; phy_disable_cca = 0x40001340; phy_enable_cca = 0x40001344; write_gain_mem = 0x40001348; bb_bss_cbw40_dig = 0x4000134c; cbw2040_cfg = 0x40001350; mac_tx_chan_offset = 0x40001354; tx_paon_set = 0x40001358; pwdet_reg_init = 0x4000135c; i2cmst_reg_init = 0x40001360; bt_gain_offset = 0x40001364; fe_reg_init = 0x40001368; mac_enable_bb = 0x4000136c; bb_wdg_cfg = 0x40001370; fe_txrx_reset = 0x40001374; set_rx_comp = 0x40001378; agc_reg_init = 0x4000137c; bb_reg_init = 0x40001380; open_i2c_xpd = 0x40001384; txiq_set_reg = 0x40001388; rxiq_set_reg = 0x4000138c; set_txclk_en = 0x40001390; set_rxclk_en = 0x40001394; bb_wdg_test_en = 0x40001398; noise_floor_auto_set = 0x4000139c; read_hw_noisefloor = 0x400013a0; iq_corr_enable = 0x400013a4; wifi_agc_sat_gain = 0x400013a8; phy_bbpll_cal = 0x400013ac; phy_ant_init = 0x400013b0; phy_set_bbfreq_init = 0x400013b4; wifi_fbw_sel = 0x400013b8; bt_filter_reg = 0x400013bc; phy_rx_sense_set = 0x400013c0; tx_state_set = 0x400013c4; phy_close_pa = 0x400013c8; phy_freq_correct = 0x400013cc; set_pbus_reg = 0x400013d0; wifi_rifs_mode_en = 0x400013d4; nrx_freq_set = 0x400013d8; fe_adc_on = 0x400013dc; phy_force_pwr_index = 0x400013e0; rom_iq_est_enable = 0x400013e4; rom_iq_est_disable = 0x400013e8; rom_bb_gain_index = 0x400013ec; rom_rfrx_gain_index = 0x400013f0; dc_iq_est = 0x400013f4; set_cal_rxdc = 0x400013f8; rxiq_get_mis = 0x400013fc; rxiq_cover_mg_mp = 0x40001400; rfcal_rxiq = 0x40001404; get_rfcal_rxiq_data = 0x40001408; get_dco_comp = 0x4000140c; pbus_rx_dco_cal = 0x40001410; rxdc_est_min = 0x40001414; pbus_rx_dco_cal_1step = 0x40001418; set_lb_txiq = 0x4000141c; set_rx_gain_cal_iq = 0x40001420; set_rx_gain_cal_dc = 0x40001424; spur_reg_write_one_tone = 0x40001428; spur_cal = 0x4000142c; spur_coef_cfg = 0x40001430; tsens_power_up = 0x40001434; tsens_read_init = 0x40001438; code_to_temp = 0x4000143c; tsens_index_to_dac = 0x40001440; tsens_index_to_offset = 0x40001444; tsens_dac_cal = 0x40001448; tsens_code_read = 0x4000144c; tsens_temp_read = 0x40001450; temp_to_power = 0x40001454; get_temp_init = 0x40001458; txbbgain_to_index = 0x4000145c; index_to_txbbgain = 0x40001460; bt_index_to_bb = 0x40001464; bt_bb_to_index = 0x40001468; bt_get_tx_gain = 0x4000146c; dig_gain_check = 0x40001470; wifi_get_tx_gain = 0x40001474; wifi_11g_rate_chg = 0x40001478; bt_chan_pwr_interp = 0x4000147c; get_rate_fcc_index = 0x40001480; get_chan_target_power = 0x40001484; get_tx_gain_value = 0x40001488; wifi_get_target_power = 0x4000148c; /* Data (.data, .bss, .rodata) */ phy_param_rom = 0x4087fce8;