menu "ESP System Settings" # Insert chip-specific cpu config rsource "./port/soc/$IDF_TARGET/Kconfig.cpu" orsource "./port/soc/$IDF_TARGET/Kconfig.cache" orsource "./port/soc/$IDF_TARGET/Kconfig.memory" orsource "./port/soc/$IDF_TARGET/Kconfig.tracemem" choice ESP_SYSTEM_PANIC prompt "Panic handler behaviour" default ESP_SYSTEM_PANIC_PRINT_REBOOT help If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is invoked. Configure the panic handler's action here. config ESP_SYSTEM_PANIC_PRINT_HALT bool "Print registers and halt" depends on !ESP_SYSTEM_GDBSTUB_RUNTIME help Outputs the relevant registers over the serial port and halt the processor. Needs a manual reset to restart. config ESP_SYSTEM_PANIC_PRINT_REBOOT bool "Print registers and reboot" depends on !ESP_SYSTEM_GDBSTUB_RUNTIME help Outputs the relevant registers over the serial port and immediately reset the processor. config ESP_SYSTEM_PANIC_SILENT_REBOOT bool "Silent reboot" depends on !ESP_SYSTEM_GDBSTUB_RUNTIME help Just resets the processor without outputting anything config ESP_SYSTEM_PANIC_GDBSTUB bool "GDBStub on panic" select ESP_GDBSTUB_ENABLED help Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem of the crash. endchoice config ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS int "Panic reboot delay (Seconds)" default 0 range 0 99 depends on ESP_SYSTEM_PANIC_PRINT_REBOOT help After the panic handler executes, you can specify a number of seconds to wait before the device reboots. config ESP_SYSTEM_SINGLE_CORE_MODE bool default n help Only initialize and use the main core. config ESP_SYSTEM_RTC_EXT_XTAL # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option # e.g. It will be selected on when RTC_CLK_SRC_EXT_CRYS is on bool default n config ESP_SYSTEM_RTC_EXT_OSC # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option # e.g. It will be selected on when ESPX_RTC_CLK_SRC_EXT_OSC is on bool default n config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES int "Bootstrap cycles for external 32kHz crystal" depends on ESP_SYSTEM_RTC_EXT_XTAL default 5 if IDF_TARGET_ESP32 default 0 range 0 32768 help To reduce the startup time of an external RTC crystal, we bootstrap it with a 32kHz square wave for a fixed number of cycles. Setting 0 will disable bootstrapping (if disabled, the crystal may take longer to start up or fail to oscillate under some conditions). If this value is too high, a faulty crystal may initially start and then fail. If this value is too low, an otherwise good crystal may not start. To accurately determine if the crystal has started, set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK bool default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE default y if IDF_TARGET_ESP32S2 default y if IDF_TARGET_ESP32C3 default y if IDF_TARGET_ESP32S3 default y if IDF_TARGET_ESP32C6 default n if IDF_TARGET_ESP32H2 # IDF-5667 default y if IDF_TARGET_ESP32P4 depends on SOC_RTC_FAST_MEM_SUPPORTED config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP bool "Enable RTC fast memory for dynamic allocations" default y depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK help This config option allows to add RTC fast memory region to system heap with capability similar to that of DRAM region but without DMA. This memory will be consumed first per heap initialization order by early startup services and scheduler related code. Speed wise RTC fast memory operates on APB clock and hence does not have much performance impact. config ESP_SYSTEM_USE_EH_FRAME bool "Generate and use eh_frame for backtracing" default n depends on IDF_TARGET_ARCH_RISCV help Generate DWARF information for each function of the project. These information will parsed and used to perform backtracing when panics occur. Activating this option will activate asynchronous frame unwinding and generation of both .eh_frame and .eh_frame_hdr sections, resulting in a bigger binary size (20% to 100% larger). The main purpose of this option is to be able to have a backtrace parsed and printed by the program itself, regardless of the serial monitor used. This option shall NOT be used for production. menu "Memory protection" config ESP_SYSTEM_PMP_IDRAM_SPLIT bool "Enable IRAM/DRAM split protection" depends on SOC_CPU_IDRAM_SPLIT_USING_PMP default "y" help If enabled, the CPU watches all the memory access and raises an exception in case of any memory violation. This feature automatically splits the SRAM memory, using PMP, into data and instruction segments and sets Read/Execute permissions for the instruction part (below given splitting address) and Read/Write permissions for the data part (above the splitting address). The memory protection is effective on all access through the IRAM0 and DRAM0 buses. config ESP_SYSTEM_MEMPROT_FEATURE bool "Enable memory protection" depends on SOC_MEMPROT_SUPPORTED default "y" help If enabled, the permission control module watches all the memory access and fires the panic handler if a permission violation is detected. This feature automatically splits the SRAM memory into data and instruction segments and sets Read/Execute permissions for the instruction part (below given splitting address) and Read/Write permissions for the data part (above the splitting address). The memory protection is effective on all access through the IRAM0 and DRAM0 buses. config ESP_SYSTEM_MEMPROT_FEATURE_LOCK depends on ESP_SYSTEM_MEMPROT_FEATURE bool "Lock memory protection settings" default "y" help Once locked, memory protection settings cannot be changed anymore. The lock is reset only on the chip startup. endmenu # Memory protection config ESP_SYSTEM_EVENT_QUEUE_SIZE int "System event queue size" default 32 help Config system event queue size in different application. config ESP_SYSTEM_EVENT_TASK_STACK_SIZE int "Event loop task stack size" default 2304 help Config system event task stack size in different application. config ESP_MAIN_TASK_STACK_SIZE int "Main task stack size" default 3584 help Configure the "main task" stack size. This is the stack of the task which calls app_main(). If app_main() returns then this task is deleted and its stack memory is freed. choice ESP_MAIN_TASK_AFFINITY prompt "Main task core affinity" default ESP_MAIN_TASK_AFFINITY_CPU0 help Configure the "main task" core affinity. This is the used core of the task which calls app_main(). If app_main() returns then this task is deleted. config ESP_MAIN_TASK_AFFINITY_CPU0 bool "CPU0" config ESP_MAIN_TASK_AFFINITY_CPU1 bool "CPU1" depends on !FREERTOS_UNICORE config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY bool "No affinity" endchoice config ESP_MAIN_TASK_AFFINITY hex default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0 default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1 default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY config ESP_MINIMAL_SHARED_STACK_SIZE int "Minimal allowed size for shared stack" default 2048 help Minimal value of size, in bytes, accepted to execute a expression with shared stack. choice ESP_CONSOLE_UART prompt "Channel for console output" default ESP_CONSOLE_UART_DEFAULT help Select where to send console output (through stdout and stderr). - Default is to use UART0 on pre-defined GPIOs. - If "Custom" is selected, UART0 or UART1 can be chosen, and any pins can be selected. - If "None" is selected, there will be no console output on any UART, except for initial output from ROM bootloader. This ROM output can be suppressed by GPIO strapping or EFUSE, refer to chip datasheet for details. - On chips with USB OTG peripheral, "USB CDC" option redirects output to the CDC port. This option uses the CDC driver in the chip ROM. This option is incompatible with TinyUSB stack. - On chips with an USB serial/JTAG debug controller, selecting the option for that redirects output to the CDC/ACM (serial port emulation) component of that device. config ESP_CONSOLE_UART_DEFAULT bool "Default: UART0" config ESP_CONSOLE_USB_CDC bool "USB CDC" # && !TINY_USB is because the ROM CDC driver is currently incompatible with TinyUSB. depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !TINY_USB config ESP_CONSOLE_USB_SERIAL_JTAG bool "USB Serial/JTAG Controller" select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32C3 #ESPTOOL-252 depends on SOC_USB_SERIAL_JTAG_SUPPORTED config ESP_CONSOLE_UART_CUSTOM bool "Custom UART" config ESP_CONSOLE_NONE bool "None" endchoice choice ESP_CONSOLE_SECONDARY depends on SOC_USB_SERIAL_JTAG_SUPPORTED prompt "Channel for console secondary output" default ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG help This secondary option supports output through other specific port like USB_SERIAL_JTAG when UART0 port as a primary is selected but not connected. This secondary output currently only supports non-blocking mode without using REPL. If you want to output in blocking mode with REPL or input through this secondary port, please change the primary config to this port in `Channel for console output` menu. config ESP_CONSOLE_SECONDARY_NONE bool "No secondary console" config ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG bool "USB_SERIAL_JTAG PORT" depends on !ESP_CONSOLE_USB_SERIAL_JTAG help This option supports output through USB_SERIAL_JTAG port when the UART0 port is not connected. The output currently only supports non-blocking mode without using the console. If you want to output in blocking mode with REPL or input through USB_SERIAL_JTAG port, please change the primary config to ESP_CONSOLE_USB_SERIAL_JTAG above. endchoice config ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED # Internal option, indicates that console USB SERIAL JTAG is used bool default y if ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG config ESP_CONSOLE_UART # Internal option, indicates that console UART is used (and not USB, for example) bool default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM choice ESP_CONSOLE_UART_NUM prompt "UART peripheral to use for console output (0-1)" depends on ESP_CONSOLE_UART_CUSTOM default ESP_CONSOLE_UART_CUSTOM_NUM_0 help This UART peripheral is used for console output from the ESP-IDF Bootloader and the app. If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. Due to an ESP32 ROM bug, UART2 is not supported for console output via esp_rom_printf. config ESP_CONSOLE_UART_CUSTOM_NUM_0 bool "UART0" config ESP_CONSOLE_UART_CUSTOM_NUM_1 bool "UART1" endchoice config ESP_CONSOLE_UART_NUM int default 0 if ESP_CONSOLE_UART_DEFAULT default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0 default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1 default 0 if ESP_CONSOLE_NONE # Temporarily workaround for serial_jtag usage. default ESP_ROM_USB_SERIAL_DEVICE_NUM if ESP_CONSOLE_USB_SERIAL_JTAG default -1 if !ESP_CONSOLE_UART config ESP_CONSOLE_UART_TX_GPIO int "UART TX on GPIO#" depends on ESP_CONSOLE_UART_CUSTOM range 0 SOC_GPIO_OUT_RANGE_MAX default 1 if IDF_TARGET_ESP32 default 20 if IDF_TARGET_ESP32C2 default 21 if IDF_TARGET_ESP32C3 default 16 if IDF_TARGET_ESP32C6 default 37 if IDF_TARGET_ESP32P4 default 24 if IDF_TARGET_ESP32H2 default 43 help This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including boot log output and default standard output and standard error of the app). If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. config ESP_CONSOLE_UART_RX_GPIO int "UART RX on GPIO#" depends on ESP_CONSOLE_UART_CUSTOM range 0 SOC_GPIO_IN_RANGE_MAX default 3 if IDF_TARGET_ESP32 default 19 if IDF_TARGET_ESP32C2 default 20 if IDF_TARGET_ESP32C3 default 17 if IDF_TARGET_ESP32C6 default 38 if IDF_TARGET_ESP32P4 default 23 if IDF_TARGET_ESP32H2 default 44 help This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including default default standard input of the app). Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART. If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. config ESP_CONSOLE_UART_BAUDRATE int prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM depends on ESP_CONSOLE_UART default 74880 if (IDF_TARGET_ESP32C2 && XTAL_FREQ_26) default 115200 range 1200 4000000 if !PM_ENABLE range 1200 1000000 if PM_ENABLE help This baud rate is used by both the ESP-IDF Bootloader and the app (including boot log output and default standard input/output/error of the app). The app's maximum baud rate depends on the UART clock source. If Power Management is disabled, the UART clock source is the APB clock and all baud rates in the available range will be sufficiently accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be accurate. If the configuration is different in the Bootloader binary compared to the app binary, UART is reconfigured after the bootloader exits and the app starts. config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE int "Size of USB CDC RX buffer" depends on ESP_CONSOLE_USB_CDC default 64 range 4 16384 help Set the size of USB CDC RX buffer. Increase the buffer size if your application is often receiving data over USB CDC. config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC" depends on ESP_CONSOLE_USB_CDC default n help If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC. Disabling this option saves about 1kB or RAM. config ESP_INT_WDT bool "Interrupt watchdog" default y help This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time, either because a task turned off interrupts and did not turn them on for a long time, or because an interrupt handler did not return. It will try to invoke the panic handler first and failing that reset the SoC. config ESP_INT_WDT_TIMEOUT_MS int "Interrupt watchdog timeout (ms)" depends on ESP_INT_WDT default 300 if !(SPIRAM && IDF_TARGET_ESP32) default 800 if (SPIRAM && IDF_TARGET_ESP32) range 10 10000 help The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate. config ESP_INT_WDT_CHECK_CPU1 bool "Also watch CPU1 tick interrupt" depends on ESP_INT_WDT && !FREERTOS_UNICORE default y help Also detect if interrupts on CPU 1 are disabled for too long. config ESP_TASK_WDT_EN bool "Enable Task Watchdog Timer" default y help The Task Watchdog Timer can be used to make sure individual tasks are still running. Enabling this option will enable the Task Watchdog Timer. It can be either initialized automatically at startup or initialized after startup (see Task Watchdog Timer API Reference) config ESP_TASK_WDT_USE_ESP_TIMER # Software implementation of Task Watchdog, handy for targets with only a single # Timer Group, such as the ESP32-C2 bool depends on ESP_TASK_WDT_EN default y if IDF_TARGET_ESP32C2 default n if !IDF_TARGET_ESP32C2 select ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD config ESP_TASK_WDT_INIT bool "Initialize Task Watchdog Timer on startup" depends on ESP_TASK_WDT_EN default y help Enabling this option will cause the Task Watchdog Timer to be initialized automatically at startup. config ESP_TASK_WDT_PANIC bool "Invoke panic handler on Task Watchdog timeout" depends on ESP_TASK_WDT_INIT default n help If this option is enabled, the Task Watchdog Timer will be configured to trigger the panic handler when it times out. This can also be configured at run time (see Task Watchdog Timer API Reference) config ESP_TASK_WDT_TIMEOUT_S int "Task Watchdog timeout period (seconds)" depends on ESP_TASK_WDT_INIT range 1 60 default 5 help Timeout period configuration for the Task Watchdog Timer in seconds. This is also configurable at run time (see Task Watchdog Timer API Reference) config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 bool "Watch CPU0 Idle Task" depends on ESP_TASK_WDT_INIT default y help If this option is enabled, the Task Watchdog Timer will watch the CPU0 Idle Task. Having the Task Watchdog watch the Idle Task allows for detection of CPU starvation as the Idle Task not being called is usually a symptom of CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household tasks depend on the Idle Task getting some runtime every now and then. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 bool "Watch CPU1 Idle Task" depends on ESP_TASK_WDT_INIT && !FREERTOS_UNICORE default y help If this option is enabled, the Task Watchdog Timer will wach the CPU1 Idle Task. config ESP_XT_WDT bool "Initialize XTAL32K watchdog timer on startup" depends on !IDF_TARGET_ESP32 && (ESP_SYSTEM_RTC_EXT_OSC || ESP_SYSTEM_RTC_EXT_XTAL) default n help This watchdog timer can detect oscillation failure of the XTAL32K_CLK. When such a failure is detected the hardware can be set up to automatically switch to BACKUP32K_CLK and generate an interrupt. config ESP_XT_WDT_TIMEOUT int "XTAL32K watchdog timeout period" depends on ESP_XT_WDT range 1 255 default 200 help Timeout period configuration for the XTAL32K watchdog timer based on RTC_CLK. config ESP_XT_WDT_BACKUP_CLK_ENABLE bool "Automatically switch to BACKUP32K_CLK when timer expires" depends on ESP_XT_WDT default y help Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when the watchdog timer expires. config ESP_PANIC_HANDLER_IRAM bool "Place panic handler code in IRAM" default n help If this option is disabled (default), the panic handler code is placed in flash not IRAM. This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor risk, if the flash cache status is also corrupted during the crash. If this option is enabled, the panic handler code (including required UART functions) is placed in IRAM. This may be necessary to debug some complex issues with crashes while flash cache is disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception is triggered. config ESP_DEBUG_STUBS_ENABLE bool "OpenOCD debug stubs" default COMPILER_OPTIMIZATION_LEVEL_DEBUG depends on !ESP32_TRAX && !ESP32S2_TRAX && !ESP32S3_TRAX help Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging stuff, e.g. GCOV data dump. config ESP_DEBUG_OCDAWARE bool "Make exception and panic handlers JTAG/OCD aware" default y select FREERTOS_DEBUG_OCDAWARE help The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and instead of panicking, have the debugger stop on the offending instruction. choice ESP_SYSTEM_CHECK_INT_LEVEL prompt "Interrupt level to use for Interrupt Watchdog and other system checks" default ESP_SYSTEM_CHECK_INT_LEVEL_4 help Interrupt level to use for Interrupt Watchdog, IPC_ISR and other system checks. config ESP_SYSTEM_CHECK_INT_LEVEL_5 bool "Level 5 interrupt" depends on IDF_TARGET_ESP32 help Using level 5 interrupt for Interrupt Watchdog, IPC_ISR and other system checks. config ESP_SYSTEM_CHECK_INT_LEVEL_4 bool "Level 4 interrupt" depends on !BTDM_CTRL_HLI help Using level 4 interrupt for Interrupt Watchdog, IPC_ISR and other system checks. endchoice # Insert chip-specific system config rsource "./port/soc/$IDF_TARGET/Kconfig.system" config ESP_SYSTEM_BROWNOUT_INTR bool default n help This config allows to trigger an interrupt when brownout detected. Software restart will be done at the end of the default callback. Two occasions need to restart the chip with interrupt so far. (1). For ESP32 version 1, brown-out reset function doesn't work (see ESP32 errata 3.4). So that we must restart from interrupt. (2). For special workflow, the chip needs do more things instead of restarting directly. This part needs to be done in callback function of interrupt. config ESP_SYSTEM_HW_STACK_GUARD bool "Hardware stack guard" depends on SOC_ASSIST_DEBUG_SUPPORTED default y help This config allows to trigger a panic interrupt when Stack Pointer register goes out of allocated stack memory bounds. config ESP_SYSTEM_BBPLL_RECALIB bool "Re-calibration BBPLL at startup" depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2 default y help This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version, which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with ESP-IDF version v5.2 and above. endmenu # ESP System Settings menu "IPC (Inter-Processor Call)" config ESP_IPC_TASK_STACK_SIZE int "Inter-Processor Call (IPC) task stack size" range 512 65536 if !APPTRACE_ENABLE range 2048 65536 if APPTRACE_ENABLE default 2048 if APPTRACE_ENABLE default 1280 if !APPTRACE_ENABLE && IDF_TARGET_ESP32S3 default 1024 help Configure the IPC tasks stack size. An IPC task runs on each core (in dual core mode), and allows for cross-core function calls. See IPC documentation for more details. The default IPC stack size should be enough for most common simple use cases. However, users can increase/decrease the stack size to their needs. config ESP_IPC_USES_CALLERS_PRIORITY bool "IPC runs at caller's priority" default y depends on !FREERTOS_UNICORE help If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0, hence IPC task will run at (configMAX_PRIORITIES - 1) priority. config ESP_IPC_ISR_ENABLE bool default y if !FREERTOS_UNICORE help The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the context of a High Priority Interrupt. The IPC ISR feature is intended for low latency execution of simple callbacks written in assembly on another CPU. Due to being run in a High Priority Interrupt, the assembly callbacks must be written with particular restrictions (see "IPC" and "High-Level Interrupt" docs for more details). endmenu # "IPC (Inter-Processor Call)