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@ -11,7 +11,7 @@ extra_default_build_targets:
|
||||
- esp32c61
|
||||
|
||||
bypass_check_test_targets:
|
||||
- esp32c61
|
||||
|
||||
#
|
||||
# These lines would
|
||||
# - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml
|
||||
|
@ -388,3 +388,17 @@ test_idf_build_apps_load_soc_caps:
|
||||
extends: .host_test_template
|
||||
script:
|
||||
- python tools/ci/check_soc_headers_load_in_idf_build_apps.py
|
||||
|
||||
test_nvs_gen_check:
|
||||
extends: .host_test_template
|
||||
artifacts:
|
||||
paths:
|
||||
- XUNIT_RESULT.xml
|
||||
- components/nvs_flash/nvs_partition_tool
|
||||
reports:
|
||||
junit: XUNIT_RESULT.xml
|
||||
variables:
|
||||
LC_ALL: C.UTF-8
|
||||
script:
|
||||
- cd ${IDF_PATH}/components/nvs_flash/nvs_partition_tool
|
||||
- pytest --noconftest test_nvs_gen_check.py --junitxml=XUNIT_RESULT.xml
|
||||
|
@ -19,6 +19,8 @@ def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
|
||||
|
||||
|
||||
@pytest.mark.supported_targets
|
||||
# TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-10983
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
|
||||
@pytest.mark.generic
|
||||
def test_app_update(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases(timeout=90)
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -28,12 +28,12 @@
|
||||
#include "bootloader_flash_priv.h"
|
||||
#include "bootloader_init.h"
|
||||
|
||||
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
|
||||
#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
|
||||
#define FLASH_SPID_IO SPI_D_GPIO_NUM
|
||||
#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
|
||||
#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
|
||||
#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
|
||||
#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0
|
||||
#define FLASH_SPIQ_IO MSPI_IOMUX_PIN_NUM_MISO
|
||||
#define FLASH_SPID_IO MSPI_IOMUX_PIN_NUM_MOSI
|
||||
#define FLASH_SPIWP_IO MSPI_IOMUX_PIN_NUM_WP
|
||||
#define FLASH_SPIHD_IO MSPI_IOMUX_PIN_NUM_HD
|
||||
|
||||
void bootloader_flash_update_id(void)
|
||||
{
|
||||
@ -98,15 +98,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
|
||||
} else {
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
|
||||
//select pin function gpio
|
||||
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
|
||||
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
|
||||
@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
|
||||
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
|
||||
return ESP32_PICO_V3_GPIO;
|
||||
default:
|
||||
return SPI_WP_GPIO_NUM;
|
||||
return MSPI_IOMUX_PIN_NUM_WP;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
@ -88,12 +88,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
// IDF-4066
|
||||
const uint32_t spiconfig = 0;
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
}
|
||||
|
@ -92,12 +92,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
|
@ -74,12 +74,12 @@ static const char *TAG = "boot.esp32c5";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -69,12 +69,12 @@ static const char *TAG = "boot.esp32c6";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -70,12 +70,12 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -70,12 +70,12 @@ static const char *TAG = "boot.esp32h2";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -66,12 +66,12 @@ static const char *TAG = "boot.esp32p4";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -94,12 +94,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
|
@ -105,12 +105,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
|
@ -48,8 +48,8 @@ void bootloader_console_init(void)
|
||||
|
||||
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
|
||||
// Some constants to make the following code less upper-case
|
||||
const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
|
||||
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
|
||||
const int uart_tx_gpio = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : UART_NUM_0_TXD_DIRECT_GPIO_NUM;
|
||||
const int uart_rx_gpio = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : UART_NUM_0_RXD_DIRECT_GPIO_NUM;
|
||||
|
||||
// Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
|
||||
esp_rom_output_set_as_console(uart_num);
|
||||
|
@ -17,16 +17,15 @@
|
||||
#include "hal/wdt_hal.h"
|
||||
|
||||
// Need to remove check and merge accordingly for ESP32C5 once key manager support added in IDF-8621
|
||||
#if SOC_KEY_MANAGER_SUPPORTED || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "soc/keymng_reg.h"
|
||||
#include "hal/key_mgr_types.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#else
|
||||
#include "hal/key_mgr_hal.h"
|
||||
#else /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#include "hal/key_mgr_ll.h"
|
||||
#include "hal/mspi_timing_tuning_ll.h"
|
||||
#endif /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif
|
||||
#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
|
||||
|
||||
#ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
|
||||
#include "soc/sensitive_reg.h"
|
||||
@ -223,17 +222,25 @@ static esp_err_t check_and_generate_encryption_keys(void)
|
||||
ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse");
|
||||
}
|
||||
// Need to remove check for ESP32C5 and merge accordingly once key manager support added in IDF-8621
|
||||
#if SOC_KEY_MANAGER_SUPPORTED || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2);
|
||||
REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
||||
REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
||||
#else
|
||||
#else /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
// Enable and reset key manager
|
||||
// To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
|
||||
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
|
||||
key_mgr_ll_enable_bus_clock(true);
|
||||
key_mgr_ll_enable_peripheral_clock(true);
|
||||
key_mgr_ll_reset_register();
|
||||
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
|
||||
};
|
||||
// Force Key Manager to use eFuse key for XTS-AES operation
|
||||
key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
_mspi_timing_ll_reset_mspi();
|
||||
#endif /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif
|
||||
#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
@ -1 +1 @@
|
||||
Subproject commit 3bb36a79cdfad65c656b9238e0d46b935775ed72
|
||||
Subproject commit 8112ca2c575c6feb32d755623f097f1b66759490
|
@ -1 +1 @@
|
||||
Subproject commit ef1dfc518572e9cda55f13906e32207b40ee280b
|
||||
Subproject commit d874f55e1132416fe18293ae1aa9ac73c40b3261
|
@ -210,6 +210,28 @@ typedef enum {
|
||||
ESP_BT_COD_MAJOR_DEV_UNCATEGORIZED = 31, /*!< Uncategorized: device not specified */
|
||||
} esp_bt_cod_major_dev_t;
|
||||
|
||||
/// Minor device class field of Class of Device for Peripheral Major Class
|
||||
typedef enum {
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_KEYBOARD = 0x10, /*!< Keyboard */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_POINTING = 0x20, /*!< Pointing */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_COMBO = 0x30, /*!< Combo
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_KEYBOARD, ESP_BT_COD_MINOR_PERIPHERAL_POINTING
|
||||
and ESP_BT_COD_MINOR_PERIPHERAL_COMBO can be OR'd with one of the
|
||||
following values to identify a multifunctional device. e.g.
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_KEYBOARD | ESP_BT_COD_MINOR_PERIPHERAL_GAMEPAD
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_POINTING | ESP_BT_COD_MINOR_PERIPHERAL_SENSING_DEVICE
|
||||
*/
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_JOYSTICK = 0x01, /*!< Joystick */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_GAMEPAD = 0x02, /*!< Gamepad */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_REMOTE_CONTROL = 0x03, /*!< Remote Control */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_SENSING_DEVICE = 0x04, /*!< Sensing Device */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_DIGITIZING_TABLET = 0x05, /*!< Digitizing Tablet */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_CARD_READER = 0x06, /*!< Card Reader */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_DIGITAL_PAN = 0x07, /*!< Digital Pan */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_HAND_SCANNER = 0x08, /*!< Hand Scanner */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_HAND_GESTURAL_INPUT = 0x09, /*!< Hand Gestural Input */
|
||||
} esp_bt_cod_minor_peripheral_t;
|
||||
|
||||
/// Bits of major device class field
|
||||
#define ESP_BT_COD_MAJOR_DEV_BIT_MASK (0x1f00) /*!< Major device bit mask */
|
||||
#define ESP_BT_COD_MAJOR_DEV_BIT_OFFSET (8) /*!< Major device bit offset */
|
||||
|
@ -1 +1 @@
|
||||
Subproject commit 071575038c771dedfe177e1c3e0bcf6f83d7094b
|
||||
Subproject commit d1f02191a1b17673ee0f539514f50d2e5fdc7863
|
@ -139,6 +139,10 @@ esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
|
||||
void
|
||||
esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
|
||||
{
|
||||
if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
||||
return;
|
||||
}
|
||||
|
||||
hci_driver_vhci_tx(data[0], data, len, HCI_DRIVER_DIR_H2C);
|
||||
}
|
||||
|
||||
|
@ -14,6 +14,7 @@ extern "C" {
|
||||
#include "esp_heap_caps.h"
|
||||
#include "esp_err.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "soc/uart_channel.h"
|
||||
|
||||
// Forward declaration. Definition in linenoise/linenoise.h.
|
||||
typedef struct linenoiseCompletions linenoiseCompletions;
|
||||
@ -88,8 +89,8 @@ typedef struct {
|
||||
{ \
|
||||
.channel = CONFIG_ESP_CONSOLE_UART_NUM, \
|
||||
.baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, \
|
||||
.tx_gpio_num = CONFIG_ESP_CONSOLE_UART_TX_GPIO, \
|
||||
.rx_gpio_num = CONFIG_ESP_CONSOLE_UART_RX_GPIO, \
|
||||
.tx_gpio_num = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : UART_NUM_0_TXD_DIRECT_GPIO_NUM, \
|
||||
.rx_gpio_num = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : UART_NUM_0_RXD_DIRECT_GPIO_NUM, \
|
||||
}
|
||||
#else
|
||||
#define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \
|
||||
|
@ -99,7 +99,7 @@
|
||||
#define TEST_DMA_CHAN_MASTER GET_DMA_CHAN(TEST_SPI_HOST)
|
||||
#define TEST_DMA_CHAN_SLAVE GET_DMA_CHAN(TEST_SLAVE_HOST)
|
||||
|
||||
#define FUNC_SPI 1
|
||||
#define FUNC_SPI SPI2_FUNC_NUM
|
||||
#define FUNC_GPIO PIN_FUNC_GPIO
|
||||
|
||||
//Delay information
|
||||
|
164
components/esp_coex/esp32c61/esp_coex_adapter.c
Normal file
164
components/esp_coex/esp32c61/esp_coex_adapter.c
Normal file
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <pthread.h>
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "freertos/portmacro.h"
|
||||
#include "esp_heap_caps.h"
|
||||
#include "esp_timer.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "esp_private/esp_clk.h"
|
||||
#include "private/esp_coexist_adapter.h"
|
||||
#include "esp32c61/rom/ets_sys.h"
|
||||
|
||||
#define TAG "esp_coex_adapter"
|
||||
|
||||
#define OSI_FUNCS_TIME_BLOCKING 0xffffffff
|
||||
|
||||
bool IRAM_ATTR esp_coex_common_env_is_chip_wrapper(void)
|
||||
{
|
||||
#ifdef CONFIG_IDF_ENV_FPGA
|
||||
return false;
|
||||
#else
|
||||
return true;
|
||||
#endif
|
||||
}
|
||||
|
||||
void *esp_coex_common_spin_lock_create_wrapper(void)
|
||||
{
|
||||
portMUX_TYPE tmp = portMUX_INITIALIZER_UNLOCKED;
|
||||
void *mux = malloc(sizeof(portMUX_TYPE));
|
||||
|
||||
if (mux) {
|
||||
memcpy(mux, &tmp, sizeof(portMUX_TYPE));
|
||||
return mux;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR esp_coex_common_int_disable_wrapper(void *wifi_int_mux)
|
||||
{
|
||||
if (xPortInIsrContext()) {
|
||||
portENTER_CRITICAL_ISR(wifi_int_mux);
|
||||
} else {
|
||||
portENTER_CRITICAL(wifi_int_mux);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_int_restore_wrapper(void *wifi_int_mux, uint32_t tmp)
|
||||
{
|
||||
if (xPortInIsrContext()) {
|
||||
portEXIT_CRITICAL_ISR(wifi_int_mux);
|
||||
} else {
|
||||
portEXIT_CRITICAL(wifi_int_mux);
|
||||
}
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void)
|
||||
{
|
||||
portYIELD_FROM_ISR();
|
||||
}
|
||||
|
||||
void *esp_coex_common_semphr_create_wrapper(uint32_t max, uint32_t init)
|
||||
{
|
||||
return (void *)xSemaphoreCreateCounting(max, init);
|
||||
}
|
||||
|
||||
void esp_coex_common_semphr_delete_wrapper(void *semphr)
|
||||
{
|
||||
vSemaphoreDelete(semphr);
|
||||
}
|
||||
|
||||
int32_t esp_coex_common_semphr_take_wrapper(void *semphr, uint32_t block_time_tick)
|
||||
{
|
||||
if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) {
|
||||
return (int32_t)xSemaphoreTake(semphr, portMAX_DELAY);
|
||||
} else {
|
||||
return (int32_t)xSemaphoreTake(semphr, block_time_tick);
|
||||
}
|
||||
}
|
||||
|
||||
int32_t esp_coex_common_semphr_give_wrapper(void *semphr)
|
||||
{
|
||||
return (int32_t)xSemaphoreGive(semphr);
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_timer_disarm_wrapper(void *timer)
|
||||
{
|
||||
ets_timer_disarm(timer);
|
||||
}
|
||||
|
||||
void esp_coex_common_timer_done_wrapper(void *ptimer)
|
||||
{
|
||||
ets_timer_done(ptimer);
|
||||
}
|
||||
|
||||
void esp_coex_common_timer_setfn_wrapper(void *ptimer, void *pfunction, void *parg)
|
||||
{
|
||||
ets_timer_setfn(ptimer, pfunction, parg);
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repeat)
|
||||
{
|
||||
ets_timer_arm_us(ptimer, us, repeat);
|
||||
}
|
||||
|
||||
uint32_t esp_coex_common_clk_slowclk_cal_get_wrapper(void)
|
||||
{
|
||||
/* The bit width of WiFi light sleep clock calibration is 12 while the one of
|
||||
* system is 19. It should shift 19 - 12 = 7.
|
||||
*/
|
||||
return (esp_clk_slowclk_cal_get() >> (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH));
|
||||
}
|
||||
|
||||
void *IRAM_ATTR esp_coex_common_malloc_internal_wrapper(size_t size)
|
||||
{
|
||||
return heap_caps_malloc(size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
|
||||
}
|
||||
|
||||
/* static wrapper */
|
||||
|
||||
static int32_t IRAM_ATTR esp_coex_semphr_take_from_isr_wrapper(void *semphr, void *hptw)
|
||||
{
|
||||
return (int32_t)xSemaphoreTakeFromISR(semphr, hptw);
|
||||
}
|
||||
|
||||
static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, void *hptw)
|
||||
{
|
||||
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
|
||||
}
|
||||
|
||||
coex_adapter_funcs_t g_coex_adapter_funcs = {
|
||||
._version = COEX_ADAPTER_VERSION,
|
||||
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
|
||||
._semphr_create = esp_coex_common_semphr_create_wrapper,
|
||||
._semphr_delete = esp_coex_common_semphr_delete_wrapper,
|
||||
._semphr_take_from_isr = esp_coex_semphr_take_from_isr_wrapper,
|
||||
._semphr_give_from_isr = esp_coex_semphr_give_from_isr_wrapper,
|
||||
._semphr_take = esp_coex_common_semphr_take_wrapper,
|
||||
._semphr_give = esp_coex_common_semphr_give_wrapper,
|
||||
._is_in_isr = xPortInIsrContext,
|
||||
._malloc_internal = esp_coex_common_malloc_internal_wrapper,
|
||||
._free = free,
|
||||
._esp_timer_get_time = esp_timer_get_time,
|
||||
._env_is_chip = esp_coex_common_env_is_chip_wrapper,
|
||||
._timer_disarm = esp_coex_common_timer_disarm_wrapper,
|
||||
._timer_done = esp_coex_common_timer_done_wrapper,
|
||||
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
|
||||
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
|
||||
._magic = COEX_ADAPTER_MAGIC,
|
||||
};
|
@ -1 +1 @@
|
||||
Subproject commit 3880b604ad7529c91fb4173da479dd9713ce1f66
|
||||
Subproject commit 6a3c4b312155e49593b5df184ffecb54404d295d
|
@ -22,7 +22,7 @@ case $IDF_TARGET in
|
||||
esp32s3)
|
||||
PREFIX=xtensa-esp32s3-elf-
|
||||
;;
|
||||
esp32c2|esp32c3|esp32c6|esp32h2|esp32c5)
|
||||
esp32c2|esp32c3|esp32c6|esp32h2|esp32c5|esp32c61)
|
||||
PREFIX=riscv32-esp-elf-
|
||||
;;
|
||||
*)
|
||||
|
@ -13,6 +13,7 @@ CONFIGS = [
|
||||
@pytest.mark.esp32c3
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32c61
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32s2
|
||||
@pytest.mark.esp32s3
|
||||
@ -27,6 +28,7 @@ def test_gpio_filter(dut: IdfDut) -> None:
|
||||
@pytest.mark.esp32c3
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32c61
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32s2
|
||||
@pytest.mark.esp32s3
|
||||
|
@ -351,8 +351,8 @@ static esp_err_t s_lp_i2c_pins_config(i2c_bus_handle_t handle)
|
||||
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
|
||||
rtc_gpio_iomux_func_sel(handle->sda_num, i2c_periph_signal[port_id].iomux_func);
|
||||
#else
|
||||
lp_gpio_connect_out_signal(handle->sda_num, i2c_periph_signal[port_id].scl_out_sig, 0, 0);
|
||||
lp_gpio_connect_in_signal(handle->sda_num, i2c_periph_signal[port_id].scl_in_sig, 0);
|
||||
lp_gpio_connect_out_signal(handle->sda_num, i2c_periph_signal[port_id].sda_out_sig, 0, 0);
|
||||
lp_gpio_connect_in_signal(handle->sda_num, i2c_periph_signal[port_id].sda_in_sig, 0);
|
||||
#endif
|
||||
|
||||
rtc_gpio_init(handle->scl_num);
|
||||
@ -366,8 +366,8 @@ static esp_err_t s_lp_i2c_pins_config(i2c_bus_handle_t handle)
|
||||
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
|
||||
rtc_gpio_iomux_func_sel(handle->scl_num, i2c_periph_signal[port_id].iomux_func);
|
||||
#else
|
||||
lp_gpio_connect_out_signal(handle->scl_num, i2c_periph_signal[port_id].sda_out_sig, 0, 0);
|
||||
lp_gpio_connect_in_signal(handle->scl_num, i2c_periph_signal[port_id].sda_in_sig, 0);
|
||||
lp_gpio_connect_out_signal(handle->scl_num, i2c_periph_signal[port_id].scl_out_sig, 0, 0);
|
||||
lp_gpio_connect_in_signal(handle->scl_num, i2c_periph_signal[port_id].scl_in_sig, 0);
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
|
@ -26,9 +26,14 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#if SOC_LP_I2C_SUPPORTED
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
#define LP_I2C_SCL_IO 4
|
||||
#define LP_I2C_SDA_IO 5
|
||||
#else
|
||||
#define LP_I2C_SCL_IO 7
|
||||
#define LP_I2C_SDA_IO 6
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define ESP_SLAVE_ADDR 0x28 /*!< ESP_I2C slave address, you can set any 7bit value */
|
||||
#define TEST_I2C_PORT 0
|
||||
|
@ -371,7 +371,7 @@ uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uin
|
||||
for (int sign = 1; bufsize % alignment != 0; aligned_frame_num += sign) {
|
||||
bufsize = aligned_frame_num * bytes_per_frame;
|
||||
/* If the buffer size exceed the max dma size */
|
||||
if (bufsize > I2S_DMA_BUFFER_MAX_SIZE) {
|
||||
if (bufsize > I2S_DMA_BUFFER_MAX_SIZE && sign == 1) {
|
||||
sign = -1; // toggle the search sign
|
||||
aligned_frame_num = dma_frame_num; // Reset the frame num
|
||||
bufsize = aligned_frame_num * bytes_per_frame; // Reset the bufsize
|
||||
|
@ -30,6 +30,10 @@ if(CONFIG_SOC_ISP_SHARPEN_SUPPORTED)
|
||||
list(APPEND srcs "src/isp_sharpen.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_ISP_COLOR_SUPPORTED)
|
||||
list(APPEND srcs "src/isp_color.c")
|
||||
endif()
|
||||
|
||||
if(NOT ${target} STREQUAL "linux")
|
||||
list(APPEND requires esp_mm)
|
||||
endif()
|
||||
|
@ -21,3 +21,4 @@
|
||||
#include "driver/isp_gamma.h"
|
||||
#include "driver/isp_hist.h"
|
||||
#include "driver/isp_sharpen.h"
|
||||
#include "driver/isp_color.h"
|
||||
|
82
components/esp_driver_isp/include/driver/isp_color.h
Normal file
82
components/esp_driver_isp/include/driver/isp_color.h
Normal file
@ -0,0 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_err.h"
|
||||
#include "driver/isp_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ISP color configurations
|
||||
*/
|
||||
typedef struct {
|
||||
isp_color_contrast_t color_contrast; /*!< The color contrast value, defines the contrast level of the image,
|
||||
* which controls the difference in luminance between the lightest and darkest parts of the image
|
||||
* Range 0 ~ 1, decimal value should be 0~127, default 1
|
||||
*/
|
||||
isp_color_saturation_t color_saturation; /*!< The color saturation value, controls the intensity of colors in the image,
|
||||
* affecting how vivid or muted the colors appear.
|
||||
* Range 0 ~ 1, decimal value should be 0~127, default 1
|
||||
*/
|
||||
uint32_t color_hue; /*!< The color hue value, based on the color wheel.
|
||||
* 0 degrees represents red, 120 degrees represents green, and 240 degrees represents blue. 360 degrees overlaps with 0 degrees
|
||||
* Range 0 ~ 360, default 0.
|
||||
*/
|
||||
int color_brightness; /*!< The color brightness value.
|
||||
* Range -128 ~ 127, default 0.
|
||||
* Negative range (-128 to -1): Decreases brightness, the smaller the value, the darker the image.
|
||||
* Zero (0): Maintains the original brightness, without adjusting the image's brightness.
|
||||
* Positive range (1 to 127): Increases brightness, the larger the value, the brighter the image.
|
||||
*/
|
||||
} esp_isp_color_config_t;
|
||||
|
||||
/**
|
||||
* @brief ISP Color configuration
|
||||
*
|
||||
* @note After calling this API, Color doesn't take into effect until `esp_isp_color_enable` is called
|
||||
* @note API is ISR available
|
||||
*
|
||||
* @param[in] proc Processor handle
|
||||
* @param[in] config Color configurations, set NULL to de-configure the ISP Color
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK On success
|
||||
* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid
|
||||
*/
|
||||
esp_err_t esp_isp_color_configure(isp_proc_handle_t proc, const esp_isp_color_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Enable ISP color function
|
||||
*
|
||||
* @param[in] proc Processor handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK On success
|
||||
* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
|
||||
* - ESP_ERR_INVALID_STATE Driver state is invalid.
|
||||
*/
|
||||
esp_err_t esp_isp_color_enable(isp_proc_handle_t proc);
|
||||
|
||||
/**
|
||||
* @brief Disable ISP color function
|
||||
*
|
||||
* @param[in] proc Processor handle
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK On success
|
||||
* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
|
||||
* - ESP_ERR_INVALID_STATE Driver state is invalid.
|
||||
*/
|
||||
esp_err_t esp_isp_color_disable(isp_proc_handle_t proc);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
@ -143,7 +143,7 @@ typedef struct {
|
||||
/**
|
||||
* @brief Prototype of ISP hist event callback
|
||||
*
|
||||
* @param[in] handle ISP hist controller handle
|
||||
* @param[in] hist_ctlr ISP hist controller handle
|
||||
* @param[in] edata ISP hist event data
|
||||
* @param[in] user_data User registered context, registered when in `esp_isp_hist_register_event_callbacks()`
|
||||
*
|
||||
|
@ -72,6 +72,7 @@ typedef struct isp_processor_t {
|
||||
isp_fsm_t bf_fsm;
|
||||
isp_fsm_t demosaic_fsm;
|
||||
isp_fsm_t sharpen_fsm;
|
||||
isp_fsm_t color_fsm;
|
||||
esp_isp_evt_cbs_t cbs;
|
||||
void *user_data;
|
||||
|
||||
|
70
components/esp_driver_isp/src/isp_color.c
Normal file
70
components/esp_driver_isp/src/isp_color.c
Normal file
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp_types.h>
|
||||
#include <sys/lock.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_check.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "driver/isp_core.h"
|
||||
#include "driver/isp_color.h"
|
||||
#include "soc/isp_periph.h"
|
||||
#include "esp_private/isp_private.h"
|
||||
|
||||
static const char *TAG = "ISP_COLOR";
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Color
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
esp_err_t esp_isp_color_configure(isp_proc_handle_t proc, const esp_isp_color_config_t *config)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
|
||||
if (config) {
|
||||
ESP_RETURN_ON_FALSE_ISR(((config->color_contrast.val <= ISP_LL_COLOR_CONTRAST_MAX) &&
|
||||
(config->color_saturation.val <= ISP_LL_COLOR_SATURATION_MAX) &&
|
||||
(config->color_hue <= ISP_LL_COLOR_HUE_MAX) &&
|
||||
(config->color_brightness >= ISP_LL_COLOR_BRIGNTNESS_MIN) &&
|
||||
(config->color_brightness <= ISP_LL_COLOR_BRIGNTNESS_MAX)), ESP_ERR_INVALID_ARG, TAG, "invalid color config");
|
||||
isp_hal_color_cfg_t color_hal_cfg = {
|
||||
.color_contrast = config->color_contrast,
|
||||
.color_saturation = config->color_saturation,
|
||||
.color_hue = config->color_hue,
|
||||
.color_brightness = config->color_brightness,
|
||||
};
|
||||
isp_hal_color_config(&(proc->hal), &color_hal_cfg);
|
||||
} else {
|
||||
isp_hal_color_config(&(proc->hal), NULL);
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_color_enable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->color_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "color is enabled already");
|
||||
|
||||
isp_ll_color_clk_enable(proc->hal.hw, true);
|
||||
isp_ll_color_enable(proc->hal.hw, true);
|
||||
proc->color_fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_color_disable(isp_proc_handle_t proc)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE(proc->color_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "color isn't enabled yet");
|
||||
|
||||
isp_ll_color_enable(proc->hal.hw, false);
|
||||
isp_ll_color_clk_enable(proc->hal.hw, false);
|
||||
proc->color_fsm = ISP_FSM_INIT;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
@ -17,4 +17,5 @@ endif()
|
||||
idf_component_register(SRCS ${srcs}
|
||||
INCLUDE_DIRS ${public_include}
|
||||
PRIV_REQUIRES "${priv_requires}"
|
||||
LDFRAGMENTS "linker.lf"
|
||||
)
|
||||
|
6
components/esp_driver_parlio/linker.lf
Normal file
6
components/esp_driver_parlio/linker.lf
Normal file
@ -0,0 +1,6 @@
|
||||
[mapping:parlio_driver_gdma]
|
||||
archive: libesp_hw_support.a
|
||||
entries:
|
||||
if PARLIO_ISR_IRAM_SAFE:
|
||||
gdma_link: gdma_link_mount_buffers (noflash)
|
||||
gdma_link: gdma_link_get_head_addr (noflash)
|
@ -34,6 +34,7 @@
|
||||
#include "esp_memory_utils.h"
|
||||
#include "esp_clk_tree.h"
|
||||
#include "esp_private/gdma.h"
|
||||
#include "esp_private/gdma_link.h"
|
||||
|
||||
static const char *TAG = "parlio-tx";
|
||||
|
||||
@ -49,8 +50,7 @@ typedef struct parlio_tx_unit_t {
|
||||
intr_handle_t intr; // allocated interrupt handle
|
||||
esp_pm_lock_handle_t pm_lock; // power management lock
|
||||
gdma_channel_handle_t dma_chan; // DMA channel
|
||||
parlio_dma_desc_t *dma_nodes; // DMA descriptor nodes
|
||||
parlio_dma_desc_t *dma_nodes_nc;// non-cached DMA descriptor nodes
|
||||
gdma_link_list_handle_t dma_link; // DMA link list handle
|
||||
size_t dma_nodes_num; // number of DMA descriptor nodes
|
||||
#if CONFIG_PM_ENABLE
|
||||
char pm_lock_name[PARLIO_PM_LOCK_NAME_LEN_MAX]; // pm lock name
|
||||
@ -123,8 +123,8 @@ static esp_err_t parlio_destroy_tx_unit(parlio_tx_unit_t *tx_unit)
|
||||
// de-register from group
|
||||
parlio_unregister_unit_from_group(&tx_unit->base);
|
||||
}
|
||||
if (tx_unit->dma_nodes) {
|
||||
free(tx_unit->dma_nodes);
|
||||
if (tx_unit->dma_link) {
|
||||
ESP_RETURN_ON_ERROR(gdma_del_link_list(tx_unit->dma_link), TAG, "delete dma link list failed");
|
||||
}
|
||||
free(tx_unit);
|
||||
return ESP_OK;
|
||||
@ -191,11 +191,19 @@ static esp_err_t parlio_tx_unit_init_dma(parlio_tx_unit_t *tx_unit)
|
||||
};
|
||||
gdma_apply_strategy(tx_unit->dma_chan, &gdma_strategy_conf);
|
||||
|
||||
// Link the descriptors
|
||||
// create DMA link list
|
||||
size_t dma_nodes_num = tx_unit->dma_nodes_num;
|
||||
for (int i = 0; i < dma_nodes_num; i++) {
|
||||
tx_unit->dma_nodes_nc[i].next = (i == dma_nodes_num - 1) ? NULL : &(tx_unit->dma_nodes[i + 1]);
|
||||
}
|
||||
gdma_link_list_config_t dma_link_config = {
|
||||
.buffer_alignment = 1,
|
||||
.item_alignment = PARLIO_DMA_DESC_ALIGNMENT,
|
||||
.num_items = dma_nodes_num,
|
||||
.flags = {
|
||||
.check_owner = true,
|
||||
},
|
||||
};
|
||||
|
||||
// throw the error to the caller
|
||||
ESP_RETURN_ON_ERROR(gdma_new_link_list(&dma_link_config, &tx_unit->dma_link), TAG, "create DMA link list failed");
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@ -280,26 +288,9 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
|
||||
|
||||
// create DMA descriptors
|
||||
// DMA descriptors must be placed in internal SRAM
|
||||
mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA;
|
||||
size_t dma_nodes_num = config->max_transfer_size / DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1;
|
||||
uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
|
||||
// the alignment should meet both the DMA and cache requirement
|
||||
size_t alignment = MAX(data_cache_line_size, PARLIO_DMA_DESC_ALIGNMENT);
|
||||
size_t dma_nodes_mem_size = ALIGN_UP(dma_nodes_num * sizeof(parlio_dma_desc_t), alignment);
|
||||
parlio_dma_desc_t *dma_nodes = heap_caps_aligned_calloc(alignment, 1, dma_nodes_mem_size, mem_caps);
|
||||
ESP_GOTO_ON_FALSE(dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no memory for DMA nodes");
|
||||
unit->dma_nodes = dma_nodes;
|
||||
unit->dma_nodes_num = dma_nodes_num;
|
||||
|
||||
// write back and then invalidate the cached dma_nodes, we will skip the cache (by non-cacheable address) when access the dma_nodes
|
||||
if (data_cache_line_size) {
|
||||
ESP_GOTO_ON_ERROR(esp_cache_msync(dma_nodes, dma_nodes_mem_size,
|
||||
ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE),
|
||||
err, TAG, "cache sync failed");
|
||||
}
|
||||
// we will use the non-cached address to manipulate the DMA descriptor, for simplicity
|
||||
unit->dma_nodes_nc = PARLIO_GET_NON_CACHED_DESC_ADDR(dma_nodes);
|
||||
|
||||
unit->max_transfer_bits = config->max_transfer_size * 8;
|
||||
unit->base.dir = PARLIO_DIR_TX;
|
||||
unit->data_width = data_width;
|
||||
@ -385,27 +376,6 @@ esp_err_t parlio_del_tx_unit(parlio_tx_unit_handle_t unit)
|
||||
return parlio_destroy_tx_unit(unit);
|
||||
}
|
||||
|
||||
static void IRAM_ATTR parlio_tx_mount_dma_data(parlio_tx_unit_t *tx_unit, const void *buffer, size_t len)
|
||||
{
|
||||
size_t prepared_length = 0;
|
||||
uint8_t *data = (uint8_t *)buffer;
|
||||
uint32_t mount_bytes = 0;
|
||||
parlio_dma_desc_t *desc_nc = tx_unit->dma_nodes_nc;
|
||||
|
||||
while (len) {
|
||||
assert(desc_nc);
|
||||
mount_bytes = len > PARLIO_MAX_ALIGNED_DMA_BUF_SIZE ? PARLIO_MAX_ALIGNED_DMA_BUF_SIZE : len;
|
||||
len -= mount_bytes;
|
||||
desc_nc->dw0.suc_eof = (len == 0); // whether the last frame
|
||||
desc_nc->dw0.size = mount_bytes;
|
||||
desc_nc->dw0.length = mount_bytes;
|
||||
desc_nc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
|
||||
desc_nc->buffer = &data[prepared_length];
|
||||
desc_nc = PARLIO_GET_NON_CACHED_DESC_ADDR(desc_nc->next);
|
||||
prepared_length += mount_bytes;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t parlio_tx_unit_wait_all_done(parlio_tx_unit_handle_t tx_unit, int timeout_ms)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(tx_unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
|
||||
@ -448,7 +418,15 @@ static void IRAM_ATTR parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio
|
||||
tx_unit->cur_trans = t;
|
||||
|
||||
// DMA transfer data based on bytes not bits, so convert the bit length to bytes, round up
|
||||
parlio_tx_mount_dma_data(tx_unit, t->payload, (t->payload_bits + 7) / 8);
|
||||
gdma_buffer_mount_config_t mount_config = {
|
||||
.buffer = (void *)t->payload,
|
||||
.length = (t->payload_bits + 7) / 8,
|
||||
.flags = {
|
||||
.mark_eof = true,
|
||||
.mark_final = true, // singly link list, mark final descriptor
|
||||
}
|
||||
};
|
||||
gdma_link_mount_buffers(tx_unit->dma_link, 0, &mount_config, 1, NULL);
|
||||
|
||||
parlio_ll_tx_reset_fifo(hal->regs);
|
||||
PARLIO_RCC_ATOMIC() {
|
||||
@ -457,7 +435,7 @@ static void IRAM_ATTR parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio
|
||||
parlio_ll_tx_set_idle_data_value(hal->regs, t->idle_value);
|
||||
parlio_ll_tx_set_trans_bit_len(hal->regs, t->payload_bits);
|
||||
|
||||
gdma_start(tx_unit->dma_chan, (intptr_t)tx_unit->dma_nodes);
|
||||
gdma_start(tx_unit->dma_chan, gdma_link_get_head_addr(tx_unit->dma_link));
|
||||
// wait until the data goes from the DMA to TX unit's FIFO
|
||||
while (parlio_ll_tx_is_ready(hal->regs) == false);
|
||||
// turn on the core clock after we start the TX unit
|
||||
|
@ -13,7 +13,6 @@
|
||||
#include "esp_timer.h"
|
||||
#include "esp_check.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/soc_pins.h"
|
||||
#include "soc/gpio_periph.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_sys.h"
|
||||
@ -28,6 +27,7 @@
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/gpio_hal.h"
|
||||
#include "hal/sdmmc_hal.h"
|
||||
#include "hal/sd_types.h"
|
||||
#include "hal/sdmmc_ll.h"
|
||||
|
||||
#define SDMMC_EVENT_QUEUE_LENGTH 32
|
||||
@ -96,25 +96,35 @@ static host_ctx_t s_host_ctx = {0};
|
||||
#endif
|
||||
|
||||
static void sdmmc_isr(void *arg);
|
||||
static void sdmmc_host_dma_init(void);
|
||||
static esp_err_t sdmmc_host_pullup_en_internal(int slot, int width);
|
||||
static bool sdmmc_host_slot_initialized(int slot);
|
||||
#if SOC_SDMMC_NUM_SLOTS >= 2
|
||||
static void sdmmc_host_change_to_slot(int slot);
|
||||
#endif
|
||||
|
||||
static void s_module_reset(void)
|
||||
{
|
||||
// reset module
|
||||
sdmmc_ll_reset_controller(s_host_ctx.hal.dev);
|
||||
sdmmc_ll_reset_dma(s_host_ctx.hal.dev);
|
||||
sdmmc_ll_reset_fifo(s_host_ctx.hal.dev);
|
||||
}
|
||||
|
||||
static bool s_is_module_reset_done(void)
|
||||
{
|
||||
bool is_done = sdmmc_ll_is_controller_reset_done(s_host_ctx.hal.dev) && sdmmc_ll_is_dma_reset_done(s_host_ctx.hal.dev) && sdmmc_ll_is_fifo_reset_done(s_host_ctx.hal.dev);
|
||||
return is_done;
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_reset(void)
|
||||
{
|
||||
// Set reset bits
|
||||
SDMMC.ctrl.controller_reset = 1;
|
||||
SDMMC.ctrl.dma_reset = 1;
|
||||
SDMMC.ctrl.fifo_reset = 1;
|
||||
s_module_reset();
|
||||
|
||||
// Wait for the reset bits to be cleared by hardware
|
||||
int64_t yield_delay_us = 100 * 1000; // initially 100ms
|
||||
int64_t t0 = esp_timer_get_time();
|
||||
int64_t t1 = 0;
|
||||
while (SDMMC.ctrl.controller_reset || SDMMC.ctrl.fifo_reset || SDMMC.ctrl.dma_reset) {
|
||||
while (!s_is_module_reset_done()) {
|
||||
t1 = esp_timer_get_time();
|
||||
if (t1 - t0 > SDMMC_HOST_RESET_TIMEOUT_US) {
|
||||
return ESP_ERR_TIMEOUT;
|
||||
@ -187,14 +197,14 @@ static esp_err_t sdmmc_host_clock_update_command(int slot)
|
||||
}
|
||||
// Sending clock update command to the CIU can generate HLE error.
|
||||
// According to the manual, this is okay and we must retry the command.
|
||||
if (SDMMC.rintsts.hle) {
|
||||
SDMMC.rintsts.hle = 1;
|
||||
if (sdmmc_ll_get_interrupt_raw(s_host_ctx.hal.dev) & SDMMC_LL_EVENT_HLE) {
|
||||
sdmmc_ll_clear_interrupt(s_host_ctx.hal.dev, SDMMC_LL_EVENT_HLE);
|
||||
repeat = true;
|
||||
break;
|
||||
}
|
||||
// When the command is accepted by CIU, start_command bit will be
|
||||
// cleared in SDMMC.cmd register.
|
||||
if (SDMMC.cmd.start_command == 0) {
|
||||
if (sdmmc_ll_is_command_taken(s_host_ctx.hal.dev)) {
|
||||
repeat = false;
|
||||
break;
|
||||
}
|
||||
@ -413,7 +423,7 @@ esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg)
|
||||
int64_t yield_delay_us = 100 * 1000; // initially 100ms
|
||||
int64_t t0 = esp_timer_get_time();
|
||||
int64_t t1 = 0;
|
||||
while (SDMMC.cmd.start_command == 1) {
|
||||
while (!sdmmc_ll_is_command_taken(s_host_ctx.hal.dev)) {
|
||||
t1 = esp_timer_get_time();
|
||||
if (t1 - t0 > SDMMC_HOST_START_CMD_TIMEOUT_US) {
|
||||
return ESP_ERR_TIMEOUT;
|
||||
@ -423,10 +433,10 @@ esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg)
|
||||
vTaskDelay(1);
|
||||
}
|
||||
}
|
||||
SDMMC.cmdarg = arg;
|
||||
sdmmc_ll_set_command_arg(s_host_ctx.hal.dev, arg);
|
||||
cmd.card_num = slot;
|
||||
cmd.start_command = 1;
|
||||
SDMMC.cmd = cmd;
|
||||
sdmmc_ll_set_command(s_host_ctx.hal.dev, cmd);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@ -440,7 +450,7 @@ static void sdmmc_host_intmask_clear_disable(void)
|
||||
static void sdmmc_host_intmask_set_enable(void)
|
||||
{
|
||||
sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, 0xffffffff, false);
|
||||
sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, SDMMC_LL_INTMASK_DEFAULT, true);
|
||||
sdmmc_ll_enable_interrupt(s_host_ctx.hal.dev, SDMMC_LL_EVENT_DEFAULT, true);
|
||||
sdmmc_ll_enable_global_interrupt(s_host_ctx.hal.dev, true);
|
||||
}
|
||||
|
||||
@ -470,7 +480,7 @@ esp_err_t sdmmc_host_init(void)
|
||||
return err;
|
||||
}
|
||||
|
||||
ESP_LOGD(TAG, "peripheral version %"PRIx32", hardware config %08"PRIx32, SDMMC.verid, SDMMC.hcon.val);
|
||||
ESP_LOGD(TAG, "peripheral version %"PRIx32", hardware config %08"PRIx32, sdmmc_ll_get_version_id(s_host_ctx.hal.dev), sdmmc_ll_get_hw_config_info(s_host_ctx.hal.dev));
|
||||
|
||||
// Clear interrupt status and set interrupt mask to known state
|
||||
sdmmc_host_intmask_clear_disable();
|
||||
@ -499,10 +509,10 @@ esp_err_t sdmmc_host_init(void)
|
||||
sdmmc_host_intmask_set_enable();
|
||||
|
||||
// Disable generation of Busy Clear Interrupt
|
||||
SDMMC.cardthrctl.busy_clr_int_en = 0;
|
||||
sdmmc_ll_enable_busy_clear_interrupt(s_host_ctx.hal.dev, false);
|
||||
|
||||
// Enable DMA
|
||||
sdmmc_host_dma_init();
|
||||
// Init DMA
|
||||
sdmmc_ll_init_dma(s_host_ctx.hal.dev);
|
||||
|
||||
// Initialize transaction handler
|
||||
ret = sdmmc_host_transaction_handler_init();
|
||||
@ -880,17 +890,14 @@ esp_err_t sdmmc_host_set_bus_width(int slot, size_t width)
|
||||
if (sdmmc_slot_info[slot].width < width) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
const uint16_t mask = BIT(slot);
|
||||
if (width == 1) {
|
||||
SDMMC.ctype.card_width_8 &= ~mask;
|
||||
SDMMC.ctype.card_width &= ~mask;
|
||||
sdmmc_ll_set_card_width(s_host_ctx.hal.dev, slot, SD_BUS_WIDTH_1_BIT);
|
||||
} else if (width == 4) {
|
||||
SDMMC.ctype.card_width_8 &= ~mask;
|
||||
SDMMC.ctype.card_width |= mask;
|
||||
sdmmc_ll_set_card_width(s_host_ctx.hal.dev, slot, SD_BUS_WIDTH_4_BIT);
|
||||
// D3 was set to GPIO high to force slave into SD mode, until 4-bit mode is set
|
||||
configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d3, sdmmc_slot_gpio_sig[slot].d3, GPIO_MODE_INPUT_OUTPUT, "d3", s_host_ctx.slot_ctx[slot].use_gpio_matrix);
|
||||
} else if (width == 8) {
|
||||
SDMMC.ctype.card_width_8 |= mask;
|
||||
sdmmc_ll_set_card_width(s_host_ctx.hal.dev, slot, SD_BUS_WIDTH_8_BIT);
|
||||
// D3 was set to GPIO high to force slave into SD mode, until 4-bit mode is set
|
||||
configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d3, sdmmc_slot_gpio_sig[slot].d3, GPIO_MODE_INPUT_OUTPUT, "d3", s_host_ctx.slot_ctx[slot].use_gpio_matrix);
|
||||
} else {
|
||||
@ -935,22 +942,9 @@ esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on)
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static void sdmmc_host_dma_init(void)
|
||||
{
|
||||
SDMMC.ctrl.dma_enable = 1;
|
||||
SDMMC.bmod.val = 0;
|
||||
SDMMC.bmod.sw_reset = 1;
|
||||
SDMMC.idinten.ni = 1;
|
||||
SDMMC.idinten.ri = 1;
|
||||
SDMMC.idinten.ti = 1;
|
||||
}
|
||||
|
||||
void sdmmc_host_dma_stop(void)
|
||||
{
|
||||
SDMMC.ctrl.use_internal_dma = 0;
|
||||
SDMMC.ctrl.dma_reset = 1;
|
||||
SDMMC.bmod.fb = 0;
|
||||
SDMMC.bmod.enable = 0;
|
||||
sdmmc_ll_stop_dma(s_host_ctx.hal.dev);
|
||||
}
|
||||
|
||||
void sdmmc_host_dma_prepare(sdmmc_desc_t *desc, size_t block_size, size_t data_size)
|
||||
@ -972,7 +966,7 @@ void sdmmc_host_dma_resume(void)
|
||||
|
||||
bool sdmmc_host_card_busy(void)
|
||||
{
|
||||
return SDMMC.status.data_busy == 1;
|
||||
return sdmmc_ll_is_card_data_busy(s_host_ctx.hal.dev);
|
||||
}
|
||||
|
||||
esp_err_t sdmmc_host_io_int_enable(int slot)
|
||||
@ -1044,12 +1038,12 @@ static void sdmmc_isr(void *arg)
|
||||
sdmmc_event_t event;
|
||||
int higher_priority_task_awoken = pdFALSE;
|
||||
|
||||
uint32_t pending = sdmmc_ll_get_intr_status(s_host_ctx.hal.dev) & 0xFFFF;
|
||||
SDMMC.rintsts.val = pending;
|
||||
uint32_t pending = sdmmc_ll_get_intr_status(s_host_ctx.hal.dev) & SDMMC_LL_SD_EVENT_MASK;
|
||||
sdmmc_ll_clear_interrupt(s_host_ctx.hal.dev, pending);
|
||||
event.sdmmc_status = pending;
|
||||
|
||||
uint32_t dma_pending = SDMMC.idsts.val;
|
||||
SDMMC.idsts.val = dma_pending;
|
||||
uint32_t dma_pending = sdmmc_ll_get_idsts_interrupt_raw(s_host_ctx.hal.dev);
|
||||
sdmmc_ll_clear_idsts_interrupt(s_host_ctx.hal.dev, dma_pending);
|
||||
event.dma_status = dma_pending & 0x1f;
|
||||
|
||||
if (pending != 0 || dma_pending != 0) {
|
||||
|
@ -6,3 +6,8 @@ set(COMPONENTS main)
|
||||
|
||||
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
|
||||
project(sdmmc_test_console)
|
||||
|
||||
message(STATUS "Checking sdmmc registers are not read-write by half-word")
|
||||
include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
|
||||
check_register_rw_half_word(SOC_MODULES "sdmmc" "pcr" "hp_sys_clkrst"
|
||||
HAL_MODULES "sdmmc")
|
||||
|
@ -9,6 +9,10 @@
|
||||
components/esp_driver_spi/test_apps/master:
|
||||
disable:
|
||||
- if: SOC_GPSPI_SUPPORTED != 1
|
||||
disable_test:
|
||||
- if: IDF_TARGET in ["esp32c61"]
|
||||
temporary: true
|
||||
reason: no multi-dev runner # TODO: [ESP32C61] IDF-10949
|
||||
<<: *spi_depends_default
|
||||
|
||||
components/esp_driver_spi/test_apps/param:
|
||||
|
@ -5,6 +5,7 @@ import pytest
|
||||
|
||||
# If `test_env` is define, should not run on generic runner
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail') # TODO: [ESP32C61] IDF-10949
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize('config', ['defaults', 'release', 'freertos_compliance', 'freertos_flash',], indirect=True)
|
||||
def test_master_single_dev(case_tester) -> None: # type: ignore
|
||||
@ -26,8 +27,8 @@ def test_master_esp_flash(case_tester) -> None: # type: ignore
|
||||
|
||||
|
||||
# if `test_env` not defined, will run on `generic_multi_device` by default
|
||||
# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5'], reason='no multi-dev runner')
|
||||
# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner')
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.generic_multi_device
|
||||
@pytest.mark.parametrize(
|
||||
|
@ -16,8 +16,8 @@ def test_param_single_dev(case_tester) -> None: # type: ignore
|
||||
|
||||
|
||||
# if `test_env` not defined, will run on `generic_multi_device` by default
|
||||
# TODO: [ESP32P4] IDF-8942 [ESP32C5] IDF-10322
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5'], reason='no multi-dev runner')
|
||||
# TODO: [ESP32P4] IDF-8942 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner')
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.generic_multi_device
|
||||
|
@ -15,8 +15,8 @@ def test_slave_single_dev(case_tester) -> None: # type: ignore
|
||||
|
||||
|
||||
# if `test_env` not defined, will run on `generic_multi_device` by default
|
||||
# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5'], reason='no multi-dev runner')
|
||||
# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner')
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.generic_multi_device
|
||||
@pytest.mark.parametrize('count, config', [(2, 'defaults'), (2, 'iram_safe')], indirect=True)
|
||||
|
@ -10,6 +10,7 @@ import pytest
|
||||
@pytest.mark.esp32c3
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32c61
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32p4
|
||||
@pytest.mark.generic
|
||||
|
@ -11,6 +11,8 @@ input_argv = {
|
||||
'esp32c6': ['uart', 'lp_uart'],
|
||||
'esp32h2': ['uart'],
|
||||
'esp32p4': ['uart', 'lp_uart'],
|
||||
'esp32c5': ['uart', 'lp_uart'],
|
||||
'esp32c61': ['uart'],
|
||||
}
|
||||
|
||||
|
||||
@ -28,9 +30,13 @@ input_argv = {
|
||||
def test_uart_single_dev(case_tester) -> None: # type: ignore
|
||||
dut = case_tester.first_dut
|
||||
chip_type = dut.app.target
|
||||
|
||||
uart_ports = input_argv.get(chip_type, [])
|
||||
assert uart_ports, f"Error: Chip type '{chip_type}' is not defined in input_argv. Aborting..."
|
||||
|
||||
for case in case_tester.test_menu:
|
||||
if 'hp-uart-only' not in case.groups:
|
||||
for uart_port in input_argv.get(chip_type, []):
|
||||
for uart_port in uart_ports:
|
||||
dut.serial.hard_reset()
|
||||
dut._get_ready()
|
||||
dut.confirm_write(case.index, expect_str=f'Running {case.name}...')
|
||||
|
@ -62,13 +62,11 @@ menu "Ethernet"
|
||||
bool "Output RMII clock from GPIO0 (Experimental!)"
|
||||
default n
|
||||
help
|
||||
GPIO0 can be set to output a pre-divided PLL clock (test only!).
|
||||
Enabling this option will configure GPIO0 to output a 50MHz clock.
|
||||
In fact this clock doesn't have directly relationship with EMAC peripheral.
|
||||
Sometimes this clock won't work well with your PHY chip. You might need to
|
||||
add some extra devices after GPIO0 (e.g. inverter).
|
||||
Note that outputting RMII clock on GPIO0 is an experimental practice.
|
||||
If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
|
||||
GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure
|
||||
GPIO0 to output a 50MHz clock. In fact this clock doesn't have directly relationship with
|
||||
EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
|
||||
WARNING: If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output
|
||||
as it would result in clock instability!
|
||||
|
||||
if !ETH_RMII_CLK_OUTPUT_GPIO0
|
||||
config ETH_RMII_CLK_OUT_GPIO
|
||||
@ -78,6 +76,8 @@ menu "Ethernet"
|
||||
default 17
|
||||
help
|
||||
Set the GPIO number to output RMII Clock.
|
||||
WARNING: If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output
|
||||
as it would result in clock instability!
|
||||
endif # !ETH_RMII_CLK_OUTPUT_GPIO0
|
||||
endif # ETH_RMII_CLK_OUTPUT
|
||||
|
||||
|
@ -51,6 +51,8 @@ typedef enum {
|
||||
/**
|
||||
* @brief RMII Clock GPIO number Options for ESP32
|
||||
*
|
||||
* @warning If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output as it would result in clock instability.
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
/**
|
||||
@ -64,10 +66,8 @@ typedef enum {
|
||||
/**
|
||||
* @brief Output RMII Clock from internal APLL Clock available at GPIO0
|
||||
*
|
||||
* @note GPIO0 can be set to output a pre-divided PLL clock (test only!). Enabling this option will configure GPIO0 to output a 50MHz clock.
|
||||
* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock won’t work well with your PHY chip.
|
||||
* You might need to add some extra devices after GPIO0 (e.g. inverter). Note that outputting RMII clock on GPIO0 is an experimental practice.
|
||||
* If you want the Ethernet to work with WiFi, don’t select GPIO0 output mode for stability.
|
||||
* @note GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure GPIO0 to output a 50MHz clock.
|
||||
* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
|
||||
*
|
||||
*/
|
||||
EMAC_APPL_CLK_OUT_GPIO = 0,
|
||||
|
@ -715,11 +715,9 @@ void bt_hidd_cb(esp_hidd_cb_event_t event, esp_hidd_cb_param_t *param)
|
||||
}
|
||||
case ESP_HIDD_SET_PROTOCOL_EVT: {
|
||||
if (param->set_protocol.protocol_mode != ESP_HIDD_UNSUPPORTED_MODE) {
|
||||
if (s_hidd_param.dev->protocol_mode == param->set_protocol.protocol_mode) {
|
||||
break;
|
||||
}
|
||||
osi_mutex_lock(&s_hidd_param.mutex, OSI_MUTEX_MAX_TIMEOUT);
|
||||
s_hidd_param.dev->protocol_mode = param->set_protocol.protocol_mode;
|
||||
s_hidd_param.dev->protocol_mode =
|
||||
param->set_protocol.protocol_mode ? ESP_HID_PROTOCOL_MODE_BOOT : ESP_HID_PROTOCOL_MODE_REPORT;
|
||||
osi_mutex_unlock(&s_hidd_param.mutex);
|
||||
cb_param.protocol_mode.dev = s_hidd_param.dev->dev;
|
||||
cb_param.protocol_mode.protocol_mode = s_hidd_param.dev->protocol_mode;
|
||||
|
@ -167,7 +167,7 @@ const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
|
||||
[11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI
|
||||
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, // NMI
|
||||
#if CONFIG_FREERTOS_CORETIMER_1
|
||||
[15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
|
||||
#else
|
||||
|
@ -13,12 +13,15 @@ choice ESP32C2_REV_MIN
|
||||
bool "Rev v1.0 (ECO1)"
|
||||
config ESP32C2_REV_MIN_1_1
|
||||
bool "Rev v1.1 (ECO2)"
|
||||
config ESP32C2_REV_MIN_200
|
||||
bool "Rev v2.0 (ECO4)"
|
||||
endchoice
|
||||
|
||||
config ESP32C2_REV_MIN_FULL
|
||||
int
|
||||
default 100 if ESP32C2_REV_MIN_1
|
||||
default 101 if ESP32C2_REV_MIN_1_1
|
||||
default 200 if ESP32C2_REV_MIN_200
|
||||
|
||||
config ESP_REV_MIN_FULL
|
||||
int
|
||||
|
@ -12,6 +12,7 @@
|
||||
#include "sdkconfig.h"
|
||||
#include "esp32c3/rom/rtc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "esp_private/rtc_clk.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "esp_rom_sys.h"
|
||||
@ -49,6 +50,8 @@ void rtc_clk_32k_enable(bool enable)
|
||||
|
||||
void rtc_clk_32k_enable_external(void)
|
||||
{
|
||||
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_PAD_HOLD_REG, RTC_CNTL_GPIO_PIN0_HOLD);
|
||||
clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL);
|
||||
}
|
||||
|
||||
|
@ -44,7 +44,7 @@ const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
|
||||
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||
/* Interrupt 14 reserved for NMI (Non-Maskable Interrupts) */
|
||||
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, 0 },
|
||||
#if CONFIG_FREERTOS_CORETIMER_1
|
||||
[15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD },
|
||||
#else
|
||||
|
@ -42,7 +42,7 @@ const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
|
||||
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||
/* Interrupt 14 reserved for NMI (Non-Maskable Interrupts) */
|
||||
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI
|
||||
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, // NMI
|
||||
[15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||
[16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
|
||||
[17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
|
||||
|
@ -12,6 +12,7 @@
|
||||
#include "sdkconfig.h"
|
||||
#include "esp32s3/rom/rtc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "esp_private/rtc_clk.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "esp_rom_sys.h"
|
||||
@ -20,6 +21,7 @@
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "esp_private/regi2c_ctrl.h"
|
||||
#include "soc/regi2c_dig_reg.h"
|
||||
#include "soc/sens_reg.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static const char *TAG = "rtc_clk";
|
||||
@ -62,8 +64,9 @@ void rtc_clk_32k_enable(bool enable)
|
||||
|
||||
void rtc_clk_32k_enable_external(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL);
|
||||
SET_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL);
|
||||
PIN_INPUT_ENABLE(IO_MUX_GPIO15_REG);
|
||||
SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_PAD_HOLD_REG, RTC_CNTL_X32P_HOLD);
|
||||
clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL);
|
||||
}
|
||||
|
||||
|
@ -26,6 +26,7 @@
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/spi_pins.h"
|
||||
#include "soc/chip_revision.h"
|
||||
#include "driver/rtc_io.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
@ -51,7 +52,6 @@
|
||||
#include "hal/rtc_hal.h"
|
||||
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "regi2c_ctrl.h" //For `REGI2C_ANA_CALI_PD_WORKAROUND`, temp
|
||||
|
||||
#include "hal/cache_hal.h"
|
||||
@ -998,12 +998,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
|
||||
#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
|
||||
/* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */
|
||||
#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359
|
||||
gpio_ll_hold_en(&GPIO, SPI_CS0_GPIO_NUM);
|
||||
gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS0);
|
||||
#endif
|
||||
#endif
|
||||
#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
|
||||
/* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */
|
||||
gpio_ll_hold_en(&GPIO, SPI_CS1_GPIO_NUM);
|
||||
gpio_ll_hold_en(&GPIO, MSPI_IOMUX_PIN_NUM_CS1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
@ -1059,11 +1059,11 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
|
||||
if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO) && (pd_flags & PMU_SLEEP_PD_TOP)) {
|
||||
#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
|
||||
#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359
|
||||
gpio_ll_hold_dis(&GPIO, SPI_CS0_GPIO_NUM);
|
||||
gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS0);
|
||||
#endif
|
||||
#endif
|
||||
#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
|
||||
gpio_ll_hold_dis(&GPIO, SPI_CS1_GPIO_NUM);
|
||||
gpio_ll_hold_dis(&GPIO, MSPI_IOMUX_PIN_NUM_CS1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
@ -9,6 +9,7 @@ from pytest_embedded import Dut
|
||||
@pytest.mark.esp32c3
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32c61
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32p4
|
||||
@pytest.mark.generic
|
||||
|
@ -26,7 +26,7 @@ def test_rtc_no_xtal32k(dut: Dut) -> None:
|
||||
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.supported_targets
|
||||
# TODO: [ESP32P4] IDF-8973 [ESP32C5] IDF-10309
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2', 'esp32p4', 'esp32c5'], reason='c6/h2/p4/c5 support TBD')
|
||||
# TODO: [ESP32P4] IDF-8973 [ESP32C5] IDF-10309 [ESP32C61] IDF-9274 IDF-10984
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], reason='support TBD')
|
||||
def test_rtc_calib(case_tester: Any) -> None:
|
||||
case_tester.run_all_multi_stage_cases()
|
||||
|
@ -52,3 +52,7 @@ components/esp_lcd/test_apps/spi_lcd:
|
||||
- esp_driver_spi
|
||||
disable:
|
||||
- if: SOC_GPSPI_SUPPORTED != 1
|
||||
disable_test:
|
||||
- if: IDF_TARGET in ["esp32c61"]
|
||||
temporary: true
|
||||
reason: test failed # TODO: ESP32C61 IDF-10953
|
||||
|
@ -5,6 +5,7 @@ from pytest_embedded import Dut
|
||||
|
||||
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail') # TODO: [ESP32C61] IDF-10953
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
|
@ -4,8 +4,8 @@ if(${idf_target} STREQUAL "linux")
|
||||
return() # This component is not supported by the POSIX/Linux simulator
|
||||
endif()
|
||||
|
||||
if(IDF_TARGET STREQUAL "esp32p4" OR IDF_TARGET STREQUAL "esp32c61")
|
||||
# TODO: IDF-7460, IDF-8851, IDF-9553
|
||||
if(IDF_TARGET STREQUAL "esp32p4")
|
||||
# TODO: IDF-7460
|
||||
idf_component_register()
|
||||
return()
|
||||
endif()
|
||||
|
24
components/esp_phy/esp32c61/include/btbb_retention_reg.h
Normal file
24
components/esp_phy/esp32c61/include/btbb_retention_reg.h
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// btbb sleep retention reg
|
||||
|
||||
#define BB_PART_0_SIZE 93
|
||||
#define BB_PART_1_SIZE 62
|
||||
#define BB_PART_2_SIZE 19
|
||||
#define BB_PART_0_ADDR 0x600A2000
|
||||
#define BB_PART_1_ADDR 0x600A2800
|
||||
#define BB_PART_2_ADDR 0x600A2C00
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
64
components/esp_phy/esp32c61/include/phy_init_data.h
Normal file
64
components/esp_phy/esp32c61/include/phy_init_data.h
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef PHY_INIT_DATA_H
|
||||
#define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
|
||||
#include <stdint.h>
|
||||
#include "esp_phy_init.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
// constrain a value between 'low' and 'high', inclusive
|
||||
#define LIMIT(val, low, high) ((val < low) ? low : (val > high) ? high : val)
|
||||
#define PHY_INIT_MAGIC "PHYINIT"
|
||||
#define PHY_INIT_MAGIC_LEN 8 // should be strlen(PHY_INIT_MAGIC) + 1
|
||||
|
||||
// define the lowest tx power as LOWEST_PHY_TX_POWER
|
||||
#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52)
|
||||
#define PHY_TX_POWER_OFFSET 2
|
||||
#define PHY_TX_POWER_NUM 14
|
||||
|
||||
#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
|
||||
#define PHY_CRC_ALGORITHM 1
|
||||
#define PHY_COUNTRY_CODE_LEN 2
|
||||
#define PHY_INIT_DATA_TYPE_OFFSET 254
|
||||
#define PHY_SUPPORT_MULTIPLE_BIN_OFFSET 253
|
||||
#endif
|
||||
|
||||
extern const char phy_init_magic_pre[];
|
||||
extern const esp_phy_init_data_t phy_init_data;
|
||||
extern const char phy_init_magic_post[];
|
||||
|
||||
#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
|
||||
/**
|
||||
* @brief PHY init data control information structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t control_info_checksum[4]; /*!< 4-byte control information checksum */
|
||||
uint8_t multiple_bin_checksum[4]; /*!< 4-byte multiple bin checksum */
|
||||
uint8_t check_algorithm; /*!< check algorithm */
|
||||
uint8_t version; /*!< PHY init data bin version */
|
||||
uint8_t number; /*!< PHY init data bin number */
|
||||
uint8_t length[2]; /*!< Length of each PHY init data bin */
|
||||
uint8_t reserved[19]; /*!< 19-byte reserved */
|
||||
} __attribute__ ((packed)) phy_control_info_data_t;
|
||||
|
||||
/**
|
||||
* @brief Country corresponds to PHY init data type structure
|
||||
*/
|
||||
typedef struct {
|
||||
char cc[PHY_COUNTRY_CODE_LEN];
|
||||
uint8_t type;
|
||||
} phy_country_to_bin_type_t;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PHY_INIT_DATA_H */
|
147
components/esp_phy/esp32c61/phy_init_data.c
Normal file
147
components/esp_phy/esp32c61/phy_init_data.c
Normal file
@ -0,0 +1,147 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "phy_init_data.h"
|
||||
|
||||
|
||||
const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_MAGIC;
|
||||
|
||||
/**
|
||||
* @brief Structure containing default recommended PHY initialization parameters.
|
||||
*/
|
||||
const esp_phy_init_data_t phy_init_data= { {
|
||||
0x1,
|
||||
0x0,
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x34),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x34),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x30),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x30),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x28),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x2c),
|
||||
LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x2c),
|
||||
0x0,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0x51
|
||||
} };
|
||||
|
||||
const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
|
BIN
components/esp_phy/esp32c61/phy_multiple_init_data.bin
Normal file
BIN
components/esp_phy/esp32c61/phy_multiple_init_data.bin
Normal file
Binary file not shown.
@ -1 +1 @@
|
||||
Subproject commit 24ea5ada50e3dd8d5d1dbc7219f22b02ba354caf
|
||||
Subproject commit a067a167a3f5581e48f4d21ed3030475dbf281da
|
@ -64,7 +64,7 @@ static _lock_t s_phy_access_lock;
|
||||
|
||||
#if SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD
|
||||
#if !SOC_PMU_SUPPORTED
|
||||
#if !CONFIG_IDF_TARGET_ESP32C5 // TODO: [ESP32C5] IDF-8667
|
||||
#if !(CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61) // TODO: [ESP32C5] IDF-8667
|
||||
static DRAM_ATTR struct {
|
||||
int count; /* power on count of wifi and bt power domain */
|
||||
_lock_t lock;
|
||||
@ -248,7 +248,6 @@ void esp_phy_enable(esp_phy_modem_t modem)
|
||||
phy_update_wifi_mac_time(false, s_phy_rf_en_ts);
|
||||
#endif
|
||||
esp_phy_common_clock_enable();
|
||||
|
||||
if (s_is_phy_calibrated == false) {
|
||||
esp_phy_load_cal_and_init();
|
||||
s_is_phy_calibrated = true;
|
||||
@ -341,7 +340,7 @@ void IRAM_ATTR esp_wifi_bt_power_domain_on(void)
|
||||
{
|
||||
#if SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD
|
||||
#if !SOC_PMU_SUPPORTED
|
||||
#if !CONFIG_IDF_TARGET_ESP32C5 // TODO: [ESP32C5] IDF-8667
|
||||
#if !(CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61) // TODO: [ESP32C5] IDF-8667
|
||||
_lock_acquire(&s_wifi_bt_pd_controller.lock);
|
||||
if (s_wifi_bt_pd_controller.count++ == 0) {
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
|
||||
@ -368,7 +367,7 @@ void esp_wifi_bt_power_domain_off(void)
|
||||
{
|
||||
#if SOC_PM_SUPPORT_MODEM_PD || SOC_PM_SUPPORT_WIFI_PD
|
||||
#if !SOC_PMU_SUPPORTED
|
||||
#if !CONFIG_IDF_TARGET_ESP32C5 // TODO: [ESP32C5] IDF-8667
|
||||
#if !(CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61) // TODO: [ESP32C5] IDF-8667
|
||||
_lock_acquire(&s_wifi_bt_pd_controller.lock);
|
||||
if (--s_wifi_bt_pd_controller.count == 0) {
|
||||
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
|
||||
|
@ -6,6 +6,7 @@ from pytest_embedded import Dut
|
||||
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='not supported yet') # TODO: [ESP32C61] IDF-9250 IDF-10985
|
||||
@pytest.mark.parametrize('config', [
|
||||
'default',
|
||||
'slp_iram_opt',
|
||||
|
@ -176,7 +176,7 @@ static void psram_gpio_config(void)
|
||||
{
|
||||
//CS1
|
||||
uint8_t cs1_io = PSRAM_CS_IO;
|
||||
if (cs1_io == SPI_CS1_GPIO_NUM) {
|
||||
if (cs1_io == MSPI_IOMUX_PIN_NUM_CS1) {
|
||||
gpio_ll_func_sel(&GPIO, cs1_io, FUNC_SPICS1_SPICS1);
|
||||
} else {
|
||||
esp_rom_gpio_connect_out_signal(cs1_io, FSPICS1_OUT_IDX, 0, 0);
|
||||
|
@ -8,7 +8,7 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/spi_pins.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -57,18 +57,18 @@ extern "C" {
|
||||
|
||||
// IO-pins for PSRAM.
|
||||
// PSRAM clock and cs IO should be configured based on hardware design.
|
||||
#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
|
||||
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
|
||||
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
|
||||
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
|
||||
#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
|
||||
#define PSRAM_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
|
||||
#define PSRAM_CS_IO MSPI_IOMUX_PIN_NUM_CS1
|
||||
#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO
|
||||
#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI
|
||||
#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP
|
||||
#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD
|
||||
|
||||
#define PSRAM_CMD_LENGTH 8
|
||||
#define PSRAM_ADDR_LENGTH 24
|
||||
#define PSRAM_CMD_LENGTH 8
|
||||
#define PSRAM_ADDR_LENGTH 24
|
||||
|
||||
#define PSRAM_CS_HOLD_VAL 1
|
||||
#define PSRAM_CS_SETUP_VAL 1
|
||||
#define PSRAM_CS_HOLD_VAL 1
|
||||
#define PSRAM_CS_SETUP_VAL 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
@ -93,11 +93,12 @@ typedef enum {
|
||||
// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
|
||||
// hardcode the flash pins as well, making this code incompatible with either a setup
|
||||
// that has the flash on non-standard pins or ESP32s with built-in flash.
|
||||
#define PSRAM_SPIQ_SD0_IO 7
|
||||
#define PSRAM_SPID_SD1_IO 8
|
||||
#define PSRAM_SPIWP_SD3_IO 10
|
||||
#define PSRAM_SPIHD_SD2_IO 9
|
||||
#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO
|
||||
#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI
|
||||
#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD
|
||||
#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP
|
||||
|
||||
// HSPI Pins
|
||||
#define FLASH_HSPI_CLK_IO 14
|
||||
#define FLASH_HSPI_CS_IO 15
|
||||
#define PSRAM_HSPI_SPIQ_SD0_IO 12
|
||||
@ -800,7 +801,7 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_
|
||||
esp_rom_gpio_connect_in_signal(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
|
||||
|
||||
//select pin function gpio
|
||||
if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
|
||||
if ((psram_io->flash_clk_io == MSPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
|
||||
//flash clock signal should come from IO MUX.
|
||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);
|
||||
} else {
|
||||
@ -909,8 +910,8 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init
|
||||
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
|
||||
psram_io.flash_clk_io = SPI_IOMUX_PIN_NUM_CLK;
|
||||
psram_io.flash_cs_io = SPI_IOMUX_PIN_NUM_CS;
|
||||
psram_io.flash_clk_io = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
psram_io.flash_cs_io = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO;
|
||||
psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO;
|
||||
psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO;
|
||||
|
@ -21,7 +21,7 @@
|
||||
#include "rom/efuse.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "soc/spi_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/spi_pins.h"
|
||||
#include "esp_private/esp_gpio_reserve.h"
|
||||
|
||||
static const char* TAG = "quad_psram";
|
||||
@ -70,15 +70,15 @@ static const char* TAG = "quad_psram";
|
||||
// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
|
||||
// hardcode the flash pins as well, making this code incompatible with either a setup
|
||||
// that has the flash on non-standard pins or ESP32s with built-in flash.
|
||||
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
|
||||
#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
|
||||
#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0
|
||||
// PSRAM clock and cs IO should be configured based on hardware design.
|
||||
#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
|
||||
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
|
||||
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
|
||||
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
|
||||
#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
|
||||
#define PSRAM_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
|
||||
#define PSRAM_CS_IO MSPI_IOMUX_PIN_NUM_CS1
|
||||
#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO
|
||||
#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI
|
||||
#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP
|
||||
#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD
|
||||
|
||||
#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
|
||||
#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
|
||||
|
@ -32,7 +32,7 @@
|
||||
#define OCT_PSRAM_ADDR_BITLEN 32
|
||||
#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
|
||||
#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
|
||||
#define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM
|
||||
#define OCT_PSRAM_CS1_IO MSPI_IOMUX_PIN_NUM_CS1
|
||||
#define OCT_PSRAM_VENDOR_ID 0xD
|
||||
|
||||
#define OCT_PSRAM_CS_SETUP_TIME 3
|
||||
|
@ -99,3 +99,16 @@ def test_psram_esp32p4(dut: Dut) -> None:
|
||||
)
|
||||
def test_psram_esp32c5(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases()
|
||||
|
||||
|
||||
@pytest.mark.esp32c61
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
[
|
||||
'esp32c61_release',
|
||||
],
|
||||
indirect=True,
|
||||
)
|
||||
def test_psram_esp32c61(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases()
|
||||
|
@ -0,0 +1,7 @@
|
||||
CONFIG_IDF_TARGET="esp32c61"
|
||||
|
||||
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
|
||||
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
|
||||
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
|
||||
|
||||
CONFIG_SPIRAM=y
|
@ -166,6 +166,11 @@ else() # Regular app build
|
||||
# For ESP32S2, inclusion of ROM driver do not depend on CONFIG_SPI_FLASH_ROM_IMPL
|
||||
rom_linker_script("spiflash_legacy")
|
||||
|
||||
elseif(target STREQUAL "esp32c2")
|
||||
if(CONFIG_ESP32C2_REV_MIN_FULL GREATER_EQUAL 200)
|
||||
rom_linker_script("eco4")
|
||||
endif()
|
||||
|
||||
elseif(target STREQUAL "esp32c3")
|
||||
|
||||
if(CONFIG_ESP32C3_REV_MIN_FULL GREATER_EQUAL 3)
|
||||
@ -190,6 +195,13 @@ else() # Regular app build
|
||||
rom_linker_script("coexist")
|
||||
rom_linker_script("net80211")
|
||||
rom_linker_script("pp")
|
||||
elseif(target STREQUAL "esp32c61")
|
||||
# esp32c61.rom.api.ld has been split to several lds by components.
|
||||
# esp32c61.rom.api.ld is still reserved to map the APIs
|
||||
rom_linker_script("phy")
|
||||
rom_linker_script("coexist")
|
||||
rom_linker_script("net80211")
|
||||
rom_linker_script("pp")
|
||||
endif()
|
||||
|
||||
|
||||
|
532
components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
Normal file
532
components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
Normal file
@ -0,0 +1,532 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group bluetooth
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
r__os_msys_find_pool = 0x40000ac0;
|
||||
r_ble_hci_ram_hs_acl_tx = 0x40000ac8;
|
||||
r_ble_hci_ram_hs_cmd_tx = 0x40000acc;
|
||||
r_ble_hci_ram_ll_acl_tx = 0x40000ad0;
|
||||
r_ble_hci_ram_ll_evt_tx = 0x40000ad4;
|
||||
r_ble_hci_trans_deinit = 0x40000af4;
|
||||
r_ble_hci_trans_env_init = 0x40000af8;
|
||||
r_ble_hci_uart_hs_acl_tx = 0x40000b10;
|
||||
r_ble_hci_uart_hs_cmd_tx = 0x40000b14;
|
||||
r_ble_hci_uart_ll_acl_tx = 0x40000b18;
|
||||
r_ble_hci_uart_ll_evt_tx = 0x40000b1c;
|
||||
r_ble_hw_driver_deinit = 0x40000b60;
|
||||
r_ble_hw_driver_env_init = 0x40000b64;
|
||||
r_ble_hw_resolv_list_get_cur_entry = 0x40000b84;
|
||||
r_ble_hw_whitelist_clear = 0x40000ba4;
|
||||
r_ble_hw_whitelist_rmv = 0x40000bb0;
|
||||
r_ble_ll_adv_deinit = 0x40000c00;
|
||||
r_ble_ll_adv_env_init = 0x40000c08;
|
||||
r_ble_ll_adv_ext_set_enable = 0x40000c10;
|
||||
r_ble_ll_adv_ext_set_param = 0x40000c14;
|
||||
r_ble_ll_adv_legacy_pdu_make = 0x40000c40;
|
||||
r_ble_ll_adv_periodic_enable = 0x40000c50;
|
||||
r_ble_ll_adv_periodic_set_data = 0x40000c5c;
|
||||
r_ble_ll_adv_remove = 0x40000c84;
|
||||
r_ble_ll_adv_reset = 0x40000c88;
|
||||
r_ble_ll_adv_rx_pkt_in = 0x40000c94;
|
||||
r_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;
|
||||
r_ble_ll_adv_set_adv_data = 0x40000cac;
|
||||
r_ble_ll_adv_set_scan_rsp_data = 0x40000cbc;
|
||||
r_ble_ll_adv_set_sched = 0x40000cc0;
|
||||
r_ble_ll_adv_sm_init = 0x40000cd4;
|
||||
r_ble_ll_adv_sync_calculate = 0x40000cf4;
|
||||
r_ble_ll_adv_sync_pdu_make = 0x40000cfc;
|
||||
r_ble_ll_arr_pool_init = 0x40000d10;
|
||||
r_ble_ll_check_scan_params = 0x40000d24;
|
||||
r_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;
|
||||
r_ble_ll_conn_create = 0x40000d58;
|
||||
r_ble_ll_conn_created = 0x40000d60;
|
||||
r_ble_ll_conn_enqueue_pkt = 0x40000d7c;
|
||||
r_ble_ll_conn_env_init = 0x40000d80;
|
||||
r_ble_ll_conn_hci_le_set_phy = 0x40000db4;
|
||||
r_ble_ll_conn_hci_set_chan_class = 0x40000dd8;
|
||||
r_ble_ll_conn_is_dev_connected = 0x40000dec;
|
||||
r_ble_ll_conn_module_deinit = 0x40000dfc;
|
||||
r_ble_ll_conn_module_init = 0x40000e00;
|
||||
r_ble_ll_conn_next_event = 0x40000e08;
|
||||
r_ble_ll_conn_prepare_tx_pdu = 0x40000e10;
|
||||
r_ble_ll_conn_rx_data_pdu = 0x40000e1c;
|
||||
r_ble_ll_conn_slave_start = 0x40000e38;
|
||||
r_ble_ll_conn_sm_new = 0x40000e40;
|
||||
r_ble_ll_conn_sm_npl_deinit = 0x40000e44;
|
||||
r_ble_ll_conn_sm_npl_init = 0x40000e48;
|
||||
r_ble_ll_ctrl_chk_proc_start = 0x40000e58;
|
||||
r_ble_ll_ctrl_conn_upd_make = 0x40000e68;
|
||||
r_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000e78;
|
||||
r_ble_ll_ctrl_proc_init = 0x40000ea8;
|
||||
r_ble_ll_ctrl_proc_start = 0x40000eb0;
|
||||
r_ble_ll_ctrl_proc_unk_rsp = 0x40000eb8;
|
||||
r_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;
|
||||
r_ble_ll_ctrl_rx_pdu = 0x40000ef0;
|
||||
r_ble_ll_ctrl_tx_done = 0x40000f30;
|
||||
r_ble_ll_deinit = 0x40000f40;
|
||||
r_ble_ll_env_init = 0x40000f48;
|
||||
r_ble_ll_ext_conn_create = 0x40000f60;
|
||||
r_ble_ll_generic_data_init = 0x40000f78;
|
||||
r_ble_ll_get_chan_to_scan = 0x40000f80;
|
||||
r_ble_ll_hci_cb_host_buf_size = 0x40000f98;
|
||||
r_ble_ll_hci_cmd_proc = 0x40000fac;
|
||||
r_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;
|
||||
r_ble_ll_hci_deinit = 0x40000fb8;
|
||||
r_ble_ll_hci_env_init = 0x40000fc0;
|
||||
r_ble_ll_hci_event_send = 0x40001004;
|
||||
r_ble_ll_hci_le_cmd_proc = 0x40001024;
|
||||
r_ble_ll_hci_le_read_local_features = 0x40001040;
|
||||
r_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;
|
||||
r_ble_ll_init = 0x400010a8;
|
||||
r_ble_ll_init_rx_pkt_in = 0x400010b4;
|
||||
r_ble_ll_mbuf_init = 0x400010dc;
|
||||
r_ble_ll_modify_sca_action = 0x400010e8;
|
||||
r_ble_ll_rand = 0x400010fc;
|
||||
r_ble_ll_rand_deinit = 0x40001104;
|
||||
r_ble_ll_rand_env_init = 0x40001108;
|
||||
r_ble_ll_read_tx_power = 0x4000112c;
|
||||
r_ble_ll_reset = 0x40001130;
|
||||
r_ble_ll_resolv_deinit = 0x4000113c;
|
||||
r_ble_ll_resolv_env_init = 0x40001148;
|
||||
r_ble_ll_resolv_gen_priv_addr = 0x4000114c;
|
||||
r_ble_ll_resolv_init = 0x4000116c;
|
||||
r_ble_ll_resolv_list_rmv = 0x4000118c;
|
||||
r_ble_ll_scan_deinit = 0x400011e4;
|
||||
r_ble_ll_scan_env_init = 0x40001208;
|
||||
r_ble_ll_scan_init = 0x40001230;
|
||||
r_ble_ll_scan_pre_process = 0x4000124c;
|
||||
r_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260;
|
||||
r_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264;
|
||||
r_ble_ll_scan_send_adv_report = 0x40001270;
|
||||
r_ble_ll_scan_set_enable = 0x40001278;
|
||||
r_ble_ll_scan_set_scan_params = 0x40001284;
|
||||
r_ble_ll_set_ext_scan_params = 0x400012a4;
|
||||
r_ble_ll_set_host_feat = 0x400012a8;
|
||||
r_ble_ll_sync_create = 0x400012d4;
|
||||
r_ble_ll_sync_deinit = 0x400012d8;
|
||||
r_ble_ll_sync_env_init = 0x400012e0;
|
||||
r_ble_ll_sync_est_event_failed = 0x400012e4;
|
||||
r_ble_ll_sync_est_event_success = 0x400012e8;
|
||||
r_ble_ll_sync_parse_ext_hdr = 0x40001334;
|
||||
r_ble_ll_sync_put_syncinfo = 0x40001344;
|
||||
r_ble_ll_sync_receive_enable = 0x40001348;
|
||||
r_ble_ll_sync_rx_pkt_in = 0x40001358;
|
||||
r_ble_ll_task = 0x4000137c;
|
||||
r_ble_ll_trace_set_func = 0x40001380;
|
||||
r_ble_ll_tx_mbuf_pducb = 0x40001394;
|
||||
r_ble_ll_tx_pkt_in = 0x40001398;
|
||||
r_ble_ll_whitelist_clear = 0x400013c8;
|
||||
r_ble_ll_whitelist_rmv = 0x400013d0;
|
||||
r_ble_ll_whitelist_search = 0x400013d4;
|
||||
r_ble_lll_adv_aux_scannable_pdu_payload_len = 0x400013dc;
|
||||
r_ble_lll_adv_drop_event = 0x40001420;
|
||||
r_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;
|
||||
r_ble_lll_adv_halt = 0x40001434;
|
||||
r_ble_lll_adv_periodic_schedule_next = 0x4000144c;
|
||||
r_ble_lll_adv_periodic_start = 0x40001450;
|
||||
r_ble_lll_adv_periodic_stop = 0x40001454;
|
||||
r_ble_lll_adv_rx_pkt_isr = 0x40001464;
|
||||
r_ble_lll_adv_sec_done = 0x40001468;
|
||||
r_ble_lll_conn_append_tx_buffer = 0x400014c8;
|
||||
r_ble_lll_conn_cth_flow_free_credit = 0x400014f0;
|
||||
r_ble_lll_conn_end = 0x400014f8;
|
||||
r_ble_lll_conn_env_deinit = 0x400014fc;
|
||||
r_ble_lll_conn_env_init = 0x40001500;
|
||||
r_ble_lll_conn_event_end = 0x40001504;
|
||||
r_ble_lll_conn_event_end_timer_cb = 0x40001508;
|
||||
r_ble_lll_conn_event_halt = 0x4000150c;
|
||||
r_ble_lll_conn_get_rx_mbuf = 0x40001528;
|
||||
r_ble_lll_conn_halt = 0x4000152c;
|
||||
r_ble_lll_conn_module_deinit = 0x40001538;
|
||||
r_ble_lll_conn_module_init = 0x4000153c;
|
||||
r_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544;
|
||||
r_ble_lll_conn_process_acked_pdu = 0x4000154c;
|
||||
r_ble_lll_conn_process_in_isr = 0x40001550;
|
||||
r_ble_lll_conn_rx_pkt_isr = 0x40001560;
|
||||
r_ble_lll_conn_set_slave_flow_control = 0x4000156c;
|
||||
r_ble_lll_conn_slave_new = 0x40001570;
|
||||
r_ble_lll_conn_update_encryption = 0x40001590;
|
||||
r_ble_lll_dtm_deinit = 0x400015a4;
|
||||
r_ble_lll_dtm_init = 0x400015b4;
|
||||
r_ble_lll_dtm_tx_create_ctx = 0x400015dc;
|
||||
r_ble_lll_init_rx_pkt_isr = 0x40001624;
|
||||
r_ble_lll_reset = 0x40001644;
|
||||
r_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;
|
||||
r_ble_lll_rfmgmt_deinit = 0x4000164c;
|
||||
r_ble_lll_rfmgmt_disable = 0x40001650;
|
||||
r_ble_lll_rfmgmt_enable = 0x40001654;
|
||||
r_ble_lll_rfmgmt_enable_now = 0x40001658;
|
||||
r_ble_lll_rfmgmt_init = 0x4000165c;
|
||||
r_ble_lll_rfmgmt_release_ev = 0x40001668;
|
||||
r_ble_lll_rfmgmt_reset = 0x4000166c;
|
||||
r_ble_lll_rfmgmt_timer_exp = 0x40001680;
|
||||
r_ble_lll_rfmgmt_timer_reschedule = 0x40001684;
|
||||
r_ble_lll_scan_aux_data_free = 0x40001698;
|
||||
r_ble_lll_scan_halt = 0x400016c4;
|
||||
r_ble_lll_scan_init = 0x400016cc;
|
||||
r_ble_lll_scan_npl_init = 0x400016d0;
|
||||
r_ble_lll_scan_process_rsp_in_isr = 0x400016e8;
|
||||
r_ble_lll_scan_restart = 0x400016f0;
|
||||
r_ble_lll_scan_rx_isr_on_aux = 0x400016f4;
|
||||
r_ble_lll_scan_rx_isr_on_legacy = 0x400016f8;
|
||||
r_ble_lll_scan_rx_pkt_isr = 0x400016fc;
|
||||
r_ble_lll_scan_stop = 0x40001710;
|
||||
r_ble_lll_scan_targeta_is_matched = 0x40001714;
|
||||
r_ble_lll_sched_conn_reschedule = 0x40001730;
|
||||
r_ble_lll_sched_deinit = 0x40001734;
|
||||
r_ble_lll_sched_env_init = 0x4000173c;
|
||||
r_ble_lll_sched_execute_check = 0x40001740;
|
||||
r_ble_lll_sched_init = 0x40001748;
|
||||
r_ble_lll_sched_sync_reschedule = 0x40001784;
|
||||
r_ble_lll_sync_event_end = 0x400017a0;
|
||||
r_ble_lll_sync_event_start_cb = 0x400017a8;
|
||||
r_ble_lll_sync_halt = 0x400017b0;
|
||||
r_ble_lll_sync_rx_pkt_isr = 0x400017c8;
|
||||
r_ble_phy_config_access_addr = 0x400017f0;
|
||||
r_ble_phy_env_init = 0x4000180c;
|
||||
r_ble_phy_init = 0x40001828;
|
||||
r_ble_phy_isr = 0x4000182c;
|
||||
r_ble_phy_module_deinit = 0x40001840;
|
||||
r_ble_phy_monitor_bb_sync = 0x40001848;
|
||||
r_ble_phy_set_adv_mode = 0x40001888;
|
||||
r_ble_phy_set_rxhdr = 0x400018a0;
|
||||
r_ble_phy_set_scan_mode = 0x400018a4;
|
||||
r_ble_phy_set_sequence_mode = 0x400018a8;
|
||||
r_ble_phy_txpower_round = 0x400018d8;
|
||||
r_ble_phy_update_conn_sequence = 0x400018e0;
|
||||
r_ble_phy_update_encryption = 0x400018e4;
|
||||
r_hal_rtc_intr_init = 0x40001960;
|
||||
r_hal_rtc_irq_handler = 0x40001964;
|
||||
r_hal_timer_deinit = 0x40001968;
|
||||
r_hal_timer_env_init = 0x40001970;
|
||||
r_hal_timer_init = 0x40001974;
|
||||
r_hal_timer_set_exp_tick = 0x40001988;
|
||||
r_hal_timer_start_at = 0x40001990;
|
||||
r_hal_timer_stop = 0x40001994;
|
||||
r_mem_split_frag = 0x400019bc;
|
||||
r_os_mbuf_append = 0x400019e0;
|
||||
r_os_memblock_put = 0x40001a48;
|
||||
r_os_mempool_init_internal = 0x40001a64;
|
||||
r_os_mempool_module_init = 0x40001a6c;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
g_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4fd8c;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group rom_pp
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esf_buf_alloc = 0x40001ae0;
|
||||
esf_buf_alloc_dynamic = 0x40001ae4;
|
||||
esf_buf_recycle = 0x40001ae8;
|
||||
hal_mac_tx_set_ppdu = 0x40001af8;
|
||||
ic_mac_deinit = 0x40001b00;
|
||||
lmacAdjustTimestamp = 0x40001b10;
|
||||
lmacDiscardMSDU = 0x40001b18;
|
||||
lmacEndFrameExchangeSequence = 0x40001b1c;
|
||||
lmacMSDUAged = 0x40001b28;
|
||||
//lmacSetTxFrame = 0x40001b4c;
|
||||
pm_check_state = 0x40001b6c;
|
||||
pm_dream = 0x40001b78;
|
||||
pm_on_beacon_rx = 0x40001ba0;
|
||||
//pm_parse_beacon = 0x40001bac;
|
||||
pm_process_tim = 0x40001bb0;
|
||||
pm_rx_beacon_process = 0x40001bb4;
|
||||
pm_rx_data_process = 0x40001bb8;
|
||||
pm_sleep = 0x40001bbc;
|
||||
//pm_tbtt_process = 0x40001bc4;
|
||||
ppAssembleAMPDU = 0x40001bcc;
|
||||
ppCalTxAMPDULength = 0x40001bd8;
|
||||
ppRxFragmentProc = 0x40001c28;
|
||||
ppRxPkt = 0x40001c2c;
|
||||
pp_coex_tx_request = 0x40001c54;
|
||||
rcGetSched = 0x40001c88;
|
||||
rcTxUpdatePer = 0x40001c94;
|
||||
rcUpdateRate = 0x40001c9c;
|
||||
wDev_AppendRxBlocks = 0x40001cdc;
|
||||
//wDev_IndicateFrame = 0x40001cec;
|
||||
wDev_ProcessFiq = 0x40001d08;
|
||||
wDev_ProcessRxSucData = 0x40001d0c;
|
||||
ppProcTxDone = 0x40001d1c;
|
||||
pm_tx_data_done_process = 0x40001d20;
|
||||
ppMapWaitTxq = 0x40001d28;
|
||||
lmacDiscardFrameExchangeSequence = 0x40001d70;
|
||||
lmacDisableTransmit = 0x40001d74;
|
||||
lmacProcessTxTimeout = 0x40001d78;
|
||||
lmacProcessTxSuccess = 0x40001d7c;
|
||||
lmacProcessTxComplete = 0x40001d8c;
|
||||
lmacProcessTxopQComplete = 0x40001dc0;
|
||||
lmacInit = 0x40001dc8;
|
||||
hal_init = 0x40001dd0;
|
||||
mac_txrx_init = 0x40001de0;
|
||||
lmac_stop_hw_txq = 0x40001df8;
|
||||
ppTxFragmentProc = 0x40001e08;
|
||||
esf_buf_setup = 0x40001e0c;
|
||||
hal_crypto_set_key_entry = 0x40001e18;
|
||||
pm_start = 0x40001e34;
|
||||
pm_stop = 0x40001e38;
|
||||
hal_set_sta_tbtt = 0x40001e4c;
|
||||
//pm_update_next_tbtt = 0x40001e50;
|
||||
pm_set_sleep_type = 0x40001e54;
|
||||
pm_tx_null_data_done_process = 0x40001eb0;
|
||||
//pm_tx_data_process = 0x40001eb4;
|
||||
pm_attach = 0x40001eb8;
|
||||
pm_coex_schm_process = 0x40001ebc;
|
||||
pm_on_probe_resp_rx = 0x40001ecc;
|
||||
pm_send_probe_stop = 0x40001edc;
|
||||
hal_sniffer_rx_set_promis = 0x40001ef4;
|
||||
hal_sniffer_set_promis_misc_pkt = 0x40001efc;
|
||||
tsf_hal_set_tbtt_start_time = 0x40001f38;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group rom_net80211
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ieee80211_ampdu_reorder = 0x40001fb0;
|
||||
ieee80211_encap_esfbuf = 0x40001fb8;
|
||||
ieee80211_output_process = 0x40001fc4;
|
||||
sta_input = 0x40001fcc;
|
||||
ieee80211_classify = 0x40001fe0;
|
||||
ieee80211_crypto_decap = 0x40001ff8;
|
||||
ieee80211_ccmp_decrypt = 0x4000200c;
|
||||
ieee80211_ccmp_encrypt = 0x40002010;
|
||||
//ieee80211_send_action_vendor_spec = 0x40002034;
|
||||
ieee80211_send_mgmt = 0x40002038;
|
||||
//ieee80211_auth_construct = 0x4000203c;
|
||||
ieee80211_deauth_construct = 0x40002040;
|
||||
ieee80211_disassoc_construct = 0x40002044;
|
||||
ieee80211_add_xrates = 0x40002058;
|
||||
//ieee80211_assoc_req_construct = 0x40002060;
|
||||
ieee80211_assoc_resp_construct = 0x40002064;
|
||||
ieee80211_timer_process = 0x4000208c;
|
||||
cnx_coexist_timeout = 0x40002090;
|
||||
//sta_recv_mgmt = 0x40002094;
|
||||
ieee80211_send_probereq = 0x4000209c;
|
||||
//sta_auth_open = 0x400020a0;
|
||||
//sta_auth_sae = 0x400020a8;
|
||||
cnx_coexist_timeout_process = 0x400020ac;
|
||||
ieee80211_add_extcap = 0x400020cc;
|
||||
//ieee80211_alloc_proberesp = 0x400020d8;
|
||||
esp_wifi_80211_tx = 0x400020f8;
|
||||
ieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;
|
||||
ieee80211_output_do = 0x4000210c;
|
||||
ieee80211_send_nulldata = 0x40002110;
|
||||
//ieee80211_setup_robust_mgmtframe = 0x40002114;
|
||||
//ieee80211_mgmt_output = 0x40002118;
|
||||
ieee80211_send_deauth = 0x40002120;
|
||||
//ieee80211_tx_mgt_cb = 0x4000212c;
|
||||
sta_rx_csa = 0x40002134;
|
||||
sta_send_sa_query_req = 0x40002138;
|
||||
sta_send_sa_query_resp = 0x4000213c;
|
||||
sta_recv_sa_query_req = 0x40002140;
|
||||
sta_recv_sa_query_resp = 0x40002144;
|
||||
ieee80211_parse_beacon = 0x40002148;
|
||||
ieee80211_match_security = 0x40002154;
|
||||
//ieee80211_parse_rsn = 0x4000215c;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
s_sa_query_retries = 0x3fcdfad8;
|
||||
s_sa_query_success = 0x3fcdfad5;
|
||||
s_trans_id = 0x3fcdfac4;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group rom_coexist
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
coex_core_event_duration_get = 0x40002178;
|
||||
coex_core_timer_idx_get = 0x4000218c;
|
||||
coex_hw_timer_tick_get = 0x400021b8;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group rom_phy
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
phy_xpd_tsens = 0x400021e8;
|
||||
bt_track_pll_cap = 0x40002534;
|
||||
tx_pwctrl_background = 0x40002548;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group eco4_systimer_hal
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
systimer_hal_deinit = 0x40002ea8;
|
||||
systimer_hal_set_tick_rate_ops = 0x40002eac;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group eco4_bluetooth
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
r_ble_ll_adv_ext_pdu_tx_len = 0x40002eb0;
|
||||
r_ble_ll_adv_ext_estimate_data_itvl = 0x40002eb4;
|
||||
r_ble_ll_adv_ext_check_data_itvl = 0x40002eb8;
|
||||
r_ble_ll_ctrl_channel_status_report_timer_cb = 0x40002ebc;
|
||||
r_ble_ll_ctrl_channel_class_enable_make = 0x40002ec0;
|
||||
r_ble_ll_ctrl_channel_class_reporting_make = 0x40002ec4;
|
||||
r_ble_ll_ctrl_rx_channel_reporting_ind = 0x40002ec8;
|
||||
r_ble_ll_ctrl_rx_channel_status_ind = 0x40002ecc;
|
||||
r_ble_ll_ctrl_channel_class_info_update = 0x40002ed0;
|
||||
r_ble_ll_adv_set_data_related_addr_change = 0x40002ed4;
|
||||
r_ble_ll_misc_additional_options_set = 0x40002ed8;
|
||||
r_ble_phy_get_txdbm_by_level = 0x40002edc;
|
||||
r_hal_timer_disable_intr = 0x40002ee0;
|
||||
r_hal_timer_enable_intr = 0x40002ee4;
|
||||
r_hal_timer_task_stop = 0x40002ee8;
|
||||
r_ble_lll_rfmgmt_env_init = 0x40002eec;
|
||||
r_ble_ll_scan_set_aux_ll_flag = 0x40002ef0;
|
||||
r_ble_ll_rf_temp_calibration = 0x40002ef4;
|
||||
r_ble_ll_adv_env_deinit = 0x40002ef8;
|
||||
r_ble_ll_conn_env_deinit = 0x40002efc;
|
||||
r_ble_ll_hci_env_deinit = 0x40002f00;
|
||||
r_ble_ll_rand_env_deinit = 0x40002f04;
|
||||
r_ble_ll_resolv_env_deinit = 0x40002f08;
|
||||
r_ble_ll_scan_env_deinit = 0x40002f0c;
|
||||
r_ble_ll_sync_env_deinit = 0x40002f10;
|
||||
r_ble_lll_rfmgmt_env_deinit = 0x40002f14;
|
||||
r_hal_timer_env_deinit = 0x40002f18;
|
||||
r_ble_ll_env_deinit = 0x40002f1c;
|
||||
r_ble_ll_generic_data_deinit = 0x40002f20;
|
||||
r_ble_hci_trans_env_deinit = 0x40002f24;
|
||||
r_ble_ll_conn_callout_env_init = 0x40002f28;
|
||||
r_ble_ll_conn_callout_env_deinit = 0x40002f2c;
|
||||
r_ble_ll_scan_callout_env_init = 0x40002f30;
|
||||
r_ble_ll_scan_callout_env_deinit = 0x40002f34;
|
||||
r_ble_ll_callout_env_init = 0x40002f38;
|
||||
r_ble_ll_callout_env_deinit = 0x40002f3c;
|
||||
r_ble_ll_resolv_callout_env_init = 0x40002f40;
|
||||
r_ble_ll_resolv_callout_env_deinit = 0x40002f44;
|
||||
r_ble_ll_get_npl_element_info = 0x40002f48;
|
||||
r_ble_rtc_wake_up_cpu_clr = 0x40002f4c;
|
||||
r_ble_ll_scan_hci_set_adv_report_flow_ctrl = 0x40002f50;
|
||||
r_ble_ll_scan_hci_update_adv_report_flow_ctrl = 0x40002f54;
|
||||
r_ble_ll_scan_send_adv_lost_report = 0x40002f58;
|
||||
r_ble_ll_scan_adv_report_cth_flow_is_enabled = 0x40002f5c;
|
||||
r_ble_ll_scan_adv_report_cth_flow_alloc_credit = 0x40002f60;
|
||||
r_ble_ll_scan_adv_report_cth_flow_free_credit = 0x40002f64;
|
||||
r_ble_ll_scan_adv_report_cth_flow_have_credit = 0x40002f68;
|
||||
r_ble_ll_scan_adv_report_lost_cnt_threshold_arrived = 0x40002f6c;
|
||||
r_ble_ll_scan_adv_report_lost_cnt_clear = 0x40002f70;
|
||||
r_ble_ll_scan_adv_report_lost_cnt_add = 0x40002f74;
|
||||
r_ble_ll_trace_hex = 0x40002f78;
|
||||
r_ble_ll_conn_calc_closest_event_cntr = 0x40002f7c;
|
||||
r_ble_ll_trace_buffer_select = 0x40002f80;
|
||||
r_ble_ll_adv_vendor_hci_legacy_adv_clear = 0x40002f84;
|
||||
r_ble_ll_conn_is_lru_compare_with_sync = 0x40002f88;
|
||||
r_ble_ll_conn_rollback_last_unmapped_chan = 0x40002f8c;
|
||||
r_ble_ll_hci_vs_csa_set = 0x40002f90;
|
||||
r_ble_ll_hci_reset = 0x40002f94;
|
||||
r_ble_ll_adv_status_check = 0x40002f98;
|
||||
r_ble_ll_conn_status_check = 0x40002f9c;
|
||||
r_ble_ll_scan_status_check = 0x40002fa0;
|
||||
r_ble_ll_sync_status_check = 0x40002fa4;
|
||||
r_ble_ll_resolv_status_check = 0x40002fa8;
|
||||
r_ble_ll_whitelist_status_check = 0x40002fac;
|
||||
r_ble_ll_adv_delay_get = 0x40002fb0;
|
||||
r_ble_ll_scan_continue_status_get = 0x40002fb4;
|
||||
r_ble_ll_default_privacy_mode_get = 0x40002fb8;
|
||||
r_ble_ll_adv_periodic_status_check = 0x40002fbc;
|
||||
r_ble_ll_sync_list_status_check = 0x40002fc0;
|
||||
r_ble_lll_rfmgmt_wake_up_ev = 0x40002fc4;
|
||||
r_ble_lll_sched_env_deinit = 0x40002fc8;
|
||||
r_ble_phy_env_deinit = 0x40002fcc;
|
||||
r_ble_hw_driver_env_deinit = 0x40002fd0;
|
||||
r_ble_lll_dtm_env_init = 0x40002fd4;
|
||||
r_ble_lll_dtm_env_deinit = 0x40002fd8;
|
||||
r_ble_lll_scan_callout_env_init = 0x40002fdc;
|
||||
r_ble_lll_scan_callout_env_deinit = 0x40002fe0;
|
||||
r_ble_lll_scan_env_init = 0x40002fe4;
|
||||
r_ble_lll_scan_env_deinit = 0x40002fe8;
|
||||
r_ble_lll_get_npl_element_info = 0x40002fec;
|
||||
r_ble_lll_conn_rxpdu_alloc = 0x40002ff0;
|
||||
r_ble_lll_scan_filter_out_useless_adv = 0x40002ff4;
|
||||
r_ble_hw_whitelist_check_in_wl = 0x40002ff8;
|
||||
r_ble_phy_stats_reset = 0x40002ffc;
|
||||
r_ble_phy_ramup_time_set = 0x40003000;
|
||||
r_ble_lll_rfmgmt_should_skip_light_sleep_check = 0x40003004;
|
||||
r_ble_phy_rx_err_record = 0x40003008;
|
||||
r_ble_lll_rfmgmt_wake_up_overhead_set = 0x4000300c;
|
||||
r_ble_lll_conn_event_delete_and_reschedule = 0x40003010;
|
||||
r_ble_lll_conn_should_reschedule = 0x40003014;
|
||||
r_ble_lll_adv_ext_event_rmvd_from_sched = 0x40003018;
|
||||
r_ble_lll_conn_process_rx_data_after_halt = 0x4000301c;
|
||||
r_ble_phy_global_rxbuf_get = 0x40003020;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
priv_config_additional_opts_ptr = 0x3fcdfa70;
|
||||
g_ble_ll_ctrl_pkt_lengths_eco4_ro = 0x3ff4fbac;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group eco4_rom_net80211
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
sta_reset_beacon_timeout = 0x40003024;
|
||||
ieee80211_post_hmac_tx = 0x40003028;
|
||||
sta_rx_eapol = 0x4000302c;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
len_dh_ie_ptr = 0x3fcdfa6c;
|
||||
g_authmode_threshold_failure_ptr = 0x3fcdfa68;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group eco4_rom_pp
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
pm_enable_dream_timer = 0x40003030;
|
||||
pm_handle_tbtt_interval = 0x40003034;
|
||||
hal_set_sta_light_sleep_wake_ahead_time = 0x40003038;
|
||||
hal_get_time_to_sta_next_tbtt = 0x4000303c;
|
||||
pm_scale_listen_interval = 0x40003040;
|
||||
pm_beacon_monitor_tbtt_start = 0x40003044;
|
||||
pm_beacon_monitor_tbtt_stop = 0x40003048;
|
||||
pm_beacon_monitor_timeout_process = 0x4000304c;
|
||||
pm_beacon_monitor_tbtt_timeout_process = 0x40003050;
|
||||
pm_on_tsf_timer = 0x40003054;
|
||||
pp_coex_tx_release = 0x40003058;
|
||||
ppRegressAmpdu = 0x4000305c;
|
||||
trc_onPPTxDone = 0x40003060;
|
||||
is_fragmented_pkt = 0x40003064;
|
||||
pm_tx_null_data_done_quick_wake_process = 0x40003068;
|
||||
pm_enable_beacon_monitor_timer = 0x4000306c;
|
||||
pm_disable_beacon_monitor_timer = 0x40003070;
|
||||
pm_beacon_offset_get_average = 0x40003074;
|
||||
pm_beacon_offset_get_expect = 0x40003078;
|
||||
pm_beacon_offset_get_params = 0x4000307c;
|
||||
pm_beacon_offset_sample_start = 0x40003080;
|
||||
pm_beacon_offset_sample = 0x40003084;
|
||||
pm_beacon_offset_reset = 0x40003088;
|
||||
pm_beacon_offset_is_sampling = 0x4000308c;
|
||||
pm_beacon_offset_is_enabled = 0x40003090;
|
||||
pm_beacon_offset_configure = 0x40003094;
|
||||
pm_beacon_offset_resample_timeout_process = 0x40003098;
|
||||
pm_beacon_offset_set_rx_beacon_standard = 0x4000309c;
|
||||
pm_beacon_offset_get_rx_beacon_success_rate = 0x400030a0;
|
||||
pm_beacon_offset_add_total_counter = 0x400030a4;
|
||||
pm_beacon_offset_add_loss_counter = 0x400030a8;
|
||||
pm_beacon_offset_check = 0x400030ac;
|
||||
pm_beacon_offset_init = 0x400030b0;
|
||||
pm_beacon_offset_deinit = 0x400030b4;
|
||||
pm_get_tbtt_count = 0x400030b8;
|
||||
pm_coex_schm_overall_period_get = 0x400030bc;
|
||||
pm_coex_pwr_update = 0x400030c0;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
s_pm_beacon_offset_ptr = 0x3fcdfa64;
|
||||
s_pm_beacon_offset_config_ptr = 0x3fcdfa60;
|
||||
s_tbttstart_ptr = 0x3fcdfa5c;
|
@ -272,7 +272,7 @@ wdev_mac_special_reg_store = 0x40000fd0;
|
||||
wdev_mac_wakeup = 0x40000fd4;
|
||||
wdev_mac_sleep = 0x40000fd8;
|
||||
wDev_ProcessFiq = 0x40000fdc;
|
||||
wDev_ProcessRxSucData = 0x40000fe0;
|
||||
/*wDev_ProcessRxSucData = 0x40000fe0;*/
|
||||
wdevProcessRxSucDataAll = 0x40000fe4;
|
||||
wdev_csi_len_align = 0x40000fe8;
|
||||
wDev_IndicateBeaconMemoryFrame = 0x40000fec;
|
||||
|
@ -40,7 +40,7 @@ ieee80211_encap_esfbuf = 0x40000ac8;
|
||||
ieee80211_is_tx_allowed = 0x40000acc;
|
||||
ieee80211_output_pending_eb = 0x40000ad0;
|
||||
ieee80211_output_process = 0x40000ad4;
|
||||
ieee80211_set_tx_desc = 0x40000ad8;
|
||||
/*ieee80211_set_tx_desc = 0x40000ad8;*/
|
||||
ieee80211_classify = 0x40000adc;
|
||||
ieee80211_copy_eb_header = 0x40000ae0;
|
||||
ieee80211_recycle_cache_eb = 0x40000ae4;
|
||||
|
@ -305,5 +305,7 @@ phy_rate_to_index = 0x400014b8;
|
||||
phy_get_target_pwr = 0x400014bc;
|
||||
phy_get_max_pwr = 0x400014c0;
|
||||
phy_get_pwr_index = 0x400014c4;
|
||||
phy_chip_set_chan_ana = 0x40005a8a;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
phy_param_rom = 0x4084fc6c;
|
||||
rom_phyFuns = 0x4084fb84;
|
||||
|
@ -76,14 +76,14 @@ lmacReachLongLimit = 0x40000c28;
|
||||
lmacReachShortLimit = 0x40000c2c;
|
||||
lmacRecycleMPDU = 0x40000c30;
|
||||
lmacRxDone = 0x40000c34;
|
||||
lmacSetTxFrame = 0x40000c38;
|
||||
/*lmacSetTxFrame = 0x40000c38;*/
|
||||
lmacTxDone = 0x40000c3c;
|
||||
lmacTxFrame = 0x40000c40;
|
||||
lmacDisableTransmit = 0x40000c44;
|
||||
lmacDiscardFrameExchangeSequence = 0x40000c48;
|
||||
lmacProcessCollision = 0x40000c4c;
|
||||
lmacProcessAckTimeout = 0x40000c50;
|
||||
lmacProcessShortRetryFail = 0x40000c54;
|
||||
/*lmacProcessShortRetryFail = 0x40000c54;*/
|
||||
lmacProcessCollisions_task = 0x40000c58;
|
||||
lmacProcessTxRtsError = 0x40000c5c;
|
||||
lmacProcessTxError = 0x40000c60;
|
||||
@ -102,7 +102,7 @@ mac_tx_set_plcp1 = 0x40000c90;
|
||||
mac_tx_set_plcp2 = 0x40000c94;
|
||||
mac_tx_set_len = 0x40000c98;
|
||||
mac_tx_set_htsig = 0x40000c9c;
|
||||
mac_tx_set_hesig = 0x40000ca0;
|
||||
/*mac_tx_set_hesig = 0x40000ca0;*/
|
||||
mac_tx_set_tb = 0x40000ca4;
|
||||
mac_tx_set_mplen = 0x40000ca8;
|
||||
mac_tx_set_txop_q = 0x40000cac;
|
||||
@ -119,7 +119,7 @@ pm_local_tsf_process = 0x40000cd4;
|
||||
pm_set_beacon_filter = 0x40000cd8;
|
||||
pm_is_in_wifi_slice_threshold = 0x40000cdc;
|
||||
pm_is_waked = 0x40000ce0;
|
||||
pm_keep_alive = 0x40000ce4;
|
||||
/*pm_keep_alive = 0x40000ce4;*/
|
||||
pm_on_beacon_rx = 0x40000ce8;
|
||||
pm_on_data_rx = 0x40000cec;
|
||||
pm_on_data_tx = 0x40000cf0;
|
||||
@ -130,14 +130,14 @@ pm_on_isr_set_twt_target = 0x40000d00;
|
||||
pm_on_isr_twt_wake = 0x40000d04;
|
||||
pm_on_tsf_timer = 0x40000d08;
|
||||
pm_on_twt_force_tx = 0x40000d0c;
|
||||
pm_parse_beacon = 0x40000d10;
|
||||
pm_process_tim = 0x40000d14;
|
||||
/*pm_parse_beacon = 0x40000d10;*/
|
||||
/*pm_process_tim = 0x40000d14;*/
|
||||
pm_rx_beacon_process = 0x40000d18;
|
||||
pm_rx_data_process = 0x40000d1c;
|
||||
pm_sleep = 0x40000d20;
|
||||
pm_sleep_for = 0x40000d24;
|
||||
pm_tbtt_process = 0x40000d28;
|
||||
pm_tx_data_done_process = 0x40000d2c;
|
||||
/*pm_tbtt_process = 0x40000d28;*/
|
||||
/*pm_tx_data_done_process = 0x40000d2c;*/
|
||||
pm_allow_tx = 0x40000d30;
|
||||
pm_extend_tbtt_adaptive_servo = 0x40000d34;
|
||||
pm_scale_listen_interval = 0x40000d38;
|
||||
@ -146,7 +146,7 @@ pm_disconnected_wake = 0x40000d40;
|
||||
/*pm_tx_data_process = 0x40000d44;*/
|
||||
pm_is_twt_awake = 0x40000d48;
|
||||
pm_enable_twt_keep_alive = 0x40000d4c;
|
||||
pm_twt_on_tsf_timer = 0x40000d50;
|
||||
/*pm_twt_on_tsf_timer = 0x40000d50;*/
|
||||
pm_twt_process = 0x40000d54;
|
||||
pm_is_twt_start = 0x40000d58;
|
||||
pm_twt_set_target_wdev_time = 0x40000d5c;
|
||||
@ -197,7 +197,7 @@ ppSearchTxQueue = 0x40000e0c;
|
||||
ppSearchTxframe = 0x40000e10;
|
||||
ppSelectNextQueue = 0x40000e14;
|
||||
ppSubFromAMPDU = 0x40000e18;
|
||||
ppTask = 0x40000e1c;
|
||||
/*ppTask = 0x40000e1c;*/
|
||||
ppTxPkt = 0x40000e20;
|
||||
ppTxProtoProc = 0x40000e24;
|
||||
ppTxqUpdateBitmap = 0x40000e28;
|
||||
@ -247,7 +247,7 @@ rcUpSched = 0x40000ed4;
|
||||
rcReachRetryLimit = 0x40000ed8;
|
||||
rcGetDCMMaxRate = 0x40000edc;
|
||||
rcGetSMPDURate = 0x40000ee0;
|
||||
rcGetRate = 0x40000ee4;
|
||||
/*rcGetRate = 0x40000ee4;*/
|
||||
rx11AXRate2AMPDULimit = 0x40000ee8;
|
||||
rx11NRate2AMPDULimit = 0x40000eec;
|
||||
rssi_margin = 0x40000ef0;
|
||||
@ -263,7 +263,7 @@ trcAmpduSetState = 0x40000f14;
|
||||
trc_set_bf_report_rate = 0x40000f18;
|
||||
trc_onPPTxDone = 0x40000f1c;
|
||||
wDevCheckBlockError = 0x40000f20;
|
||||
wDev_AppendRxBlocks = 0x40000f24;
|
||||
/*wDev_AppendRxBlocks = 0x40000f24;*/
|
||||
wDev_DiscardFrame = 0x40000f28;
|
||||
wDev_GetNoiseFloor = 0x40000f2c;
|
||||
wDev_IndicateAmpdu = 0x40000f30;
|
||||
@ -275,7 +275,7 @@ wdev_mac_special_reg_store = 0x40000f44;
|
||||
wdev_mac_wakeup = 0x40000f48;
|
||||
wdev_mac_sleep = 0x40000f4c;
|
||||
wDev_ProcessFiq = 0x40000f50;
|
||||
wDev_ProcessRxSucData = 0x40000f54;
|
||||
/*wDev_ProcessRxSucData = 0x40000f54;*/
|
||||
wdevProcessRxSucDataAll = 0x40000f58;
|
||||
wdev_csi_len_align = 0x40000f5c;
|
||||
wDev_IndicateBeaconMemoryFrame = 0x40000f60;
|
||||
|
@ -5,6 +5,7 @@ from pytest_embedded import Dut
|
||||
|
||||
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='support TBD') # TODO [ESP32C61] IDF-9257 IDF10986
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
|
@ -9,6 +9,7 @@ from pytest_embedded import Dut
|
||||
@pytest.mark.esp32s3
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32c61
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32p4
|
||||
@pytest.mark.generic
|
||||
|
@ -4,4 +4,4 @@ components/esp_security/test_apps/crypto_drivers:
|
||||
disable:
|
||||
- if: IDF_TARGET in ["esp32c61"]
|
||||
temporary: true
|
||||
reason: Support for ESP32C6 is yet to be added.
|
||||
reason: Support for ESP32C61 is yet to be added.
|
||||
|
@ -5,6 +5,7 @@ from pytest_embedded import Dut
|
||||
|
||||
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='Support for ESP32C61 is yet to be added.') # TODO: [ESP32C61] IDF-10987
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
[
|
||||
|
@ -317,19 +317,20 @@ menu "ESP System Settings"
|
||||
config ESP_CONSOLE_UART_TX_GPIO
|
||||
int "UART TX on GPIO<num>"
|
||||
depends on ESP_CONSOLE_UART_CUSTOM
|
||||
range 0 SOC_GPIO_OUT_RANGE_MAX
|
||||
range -1 SOC_GPIO_OUT_RANGE_MAX
|
||||
# Specific value for old targets for compatibility. No need to add for new targets.
|
||||
default 1 if IDF_TARGET_ESP32
|
||||
default 43 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
|
||||
default 20 if IDF_TARGET_ESP32C2
|
||||
default 21 if IDF_TARGET_ESP32C3
|
||||
default 10 if IDF_TARGET_ESP32C5
|
||||
default 16 if IDF_TARGET_ESP32C6
|
||||
default 5 if IDF_TARGET_ESP32C61
|
||||
default 37 if IDF_TARGET_ESP32P4
|
||||
default 24 if IDF_TARGET_ESP32H2
|
||||
default 43
|
||||
default -1
|
||||
help
|
||||
This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
|
||||
boot log output and default standard output and standard error of the app).
|
||||
boot log output and default standard output and standard error of the app). Value -1 means to
|
||||
continue using the default console UART TX pin.
|
||||
|
||||
If the configuration is different in the Bootloader binary compared to the app binary, UART
|
||||
is reconfigured after the bootloader exits and the app starts.
|
||||
@ -337,19 +338,20 @@ menu "ESP System Settings"
|
||||
config ESP_CONSOLE_UART_RX_GPIO
|
||||
int "UART RX on GPIO<num>"
|
||||
depends on ESP_CONSOLE_UART_CUSTOM
|
||||
range 0 SOC_GPIO_IN_RANGE_MAX
|
||||
range -1 SOC_GPIO_IN_RANGE_MAX
|
||||
# Specific value for old targets for compatibility. No need to add for new targets.
|
||||
default 3 if IDF_TARGET_ESP32
|
||||
default 44 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
|
||||
default 19 if IDF_TARGET_ESP32C2
|
||||
default 20 if IDF_TARGET_ESP32C3
|
||||
default 11 if IDF_TARGET_ESP32C5
|
||||
default 17 if IDF_TARGET_ESP32C6
|
||||
default 4 if IDF_TARGET_ESP32C61
|
||||
default 38 if IDF_TARGET_ESP32P4
|
||||
default 23 if IDF_TARGET_ESP32H2
|
||||
default 44
|
||||
default -1
|
||||
help
|
||||
This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
|
||||
default default standard input of the app).
|
||||
This GPIO is used for console UART RX input in the ESP-IDF Bootloader and the app (including
|
||||
default standard input of the app). Value -1 means to continue using the default console UART
|
||||
RX pin.
|
||||
|
||||
Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
|
||||
|
||||
|
@ -55,7 +55,7 @@ esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
|
||||
|
||||
#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
|
||||
esp_rom_printf("esp_backtrace_print: Print CPU %d (current core) backtrace\n", current_core);
|
||||
esp_eh_frame_print_backtrace(&frame);
|
||||
esp_eh_frame_print_backtrace(frame);
|
||||
#else // CONFIG_ESP_SYSTEM_USE_EH_FRAME
|
||||
esp_rom_printf("esp_backtrace_print: Print CPU %d (current core) registers\n", current_core);
|
||||
panic_prepare_frame_from_ctx(&backtrace_frame);
|
||||
|
@ -71,8 +71,8 @@
|
||||
#include "soc/hp_sys_clkrst_reg.h"
|
||||
#endif
|
||||
|
||||
#if SOC_KEY_MANAGER_SUPPORTED
|
||||
#include "hal/key_mgr_hal.h"
|
||||
#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
|
||||
#include "hal/key_mgr_ll.h"
|
||||
#endif
|
||||
|
||||
#include "esp_private/rtc_clk.h"
|
||||
@ -309,13 +309,22 @@ static void start_other_core(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if SOC_KEY_MANAGER_SUPPORTED
|
||||
// The following operation makes the Key Manager to use eFuse key for ECDSA and XTS-AES operation by default
|
||||
// This is to keep the default behavior same as the other chips
|
||||
// If the Key Manager configuration is already locked then following operation does not have any effect
|
||||
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
|
||||
// Enable key manager clock
|
||||
// Using ll APIs which do not require critical section
|
||||
_key_mgr_ll_enable_bus_clock(true);
|
||||
_key_mgr_ll_enable_peripheral_clock(true);
|
||||
#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
|
||||
key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
#endif
|
||||
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY
|
||||
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
#endif
|
||||
#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY */
|
||||
|
||||
ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
|
||||
|
||||
bool cpus_up = false;
|
||||
|
@ -5,6 +5,7 @@ from pytest_embedded import Dut
|
||||
|
||||
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail') # TODO: IDF-10954
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
[
|
||||
|
@ -388,6 +388,7 @@ TEST_CASE("esp_timer for very short intervals", "[esp_timer]")
|
||||
vTaskDelay(3); // wait for the esp_timer task to delete all timers
|
||||
}
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-10955, test fail
|
||||
TEST_CASE("esp_timer_get_time call takes less than 1us", "[esp_timer]")
|
||||
{
|
||||
int64_t begin = esp_timer_get_time();
|
||||
@ -399,6 +400,7 @@ TEST_CASE("esp_timer_get_time call takes less than 1us", "[esp_timer]")
|
||||
int ns_per_call = (int)((end - begin) * 1000 / iter_count);
|
||||
TEST_PERFORMANCE_LESS_THAN(ESP_TIMER_GET_TIME_PER_CALL, "%dns", ns_per_call);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int64_t IRAM_ATTR __attribute__((noinline)) get_clock_diff(void)
|
||||
{
|
||||
|
@ -49,6 +49,9 @@
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#include "private/esp_modem_wrapper.h"
|
||||
#if __has_include("esp_psram.h")
|
||||
#include "esp_psram.h"
|
||||
#endif
|
||||
|
||||
#define TAG "esp_adapter"
|
||||
|
||||
@ -260,36 +263,31 @@ static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex)
|
||||
|
||||
static void * queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
|
||||
{
|
||||
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
|
||||
/*
|
||||
* Since release/v5.1, FreeRTOS has been updated to always use internal memory (i.e., DRAM)
|
||||
* for dynamic memory allocation. Calling FreeRTOS creation functions (e.g., xTaskCreate(), xQueueCreate())
|
||||
* will guarantee that the memory allocated for those tasks/objects is from internal memory.
|
||||
* For more details, please refer to the Migration Guide in release/v5.1.
|
||||
*/
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
/* Use xQueueCreateWithCaps() to allocate from SPIRAM */
|
||||
return (void *)xQueueCreateWithCaps(queue_len, item_size, MALLOC_CAP_SPIRAM);
|
||||
#else
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
#endif
|
||||
#else
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
#endif
|
||||
StaticQueue_t *queue_buffer = heap_caps_malloc_prefer(sizeof(StaticQueue_t) + (queue_len * item_size), 2,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
if (!queue_buffer) {
|
||||
return NULL;
|
||||
}
|
||||
QueueHandle_t queue_handle = xQueueCreateStatic(queue_len, item_size, (uint8_t *)queue_buffer + sizeof(StaticQueue_t),
|
||||
queue_buffer);
|
||||
if (!queue_handle) {
|
||||
free(queue_buffer);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (void *)queue_handle;
|
||||
}
|
||||
|
||||
static void queue_delete_wrapper(void *queue)
|
||||
{
|
||||
if (queue) {
|
||||
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
vQueueDeleteWithCaps(queue);
|
||||
#else
|
||||
StaticQueue_t *queue_buffer = NULL;
|
||||
xQueueGetStaticBuffers(queue, NULL, &queue_buffer);
|
||||
vQueueDelete(queue);
|
||||
#endif
|
||||
#else
|
||||
vQueueDelete(queue);
|
||||
#endif
|
||||
if (queue_buffer) {
|
||||
free(queue_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -63,17 +63,29 @@ extern void wifi_apb80m_release(void);
|
||||
|
||||
IRAM_ATTR void *wifi_malloc(size_t size)
|
||||
{
|
||||
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
|
||||
return heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
#else
|
||||
return malloc(size);
|
||||
#endif
|
||||
}
|
||||
|
||||
IRAM_ATTR void *wifi_realloc(void *ptr, size_t size)
|
||||
{
|
||||
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
|
||||
return heap_caps_realloc_prefer(ptr, size, 2, MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
#else
|
||||
return realloc(ptr, size);
|
||||
#endif
|
||||
}
|
||||
|
||||
IRAM_ATTR void *wifi_calloc(size_t n, size_t size)
|
||||
{
|
||||
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
|
||||
return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
#else
|
||||
return calloc(n, size);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void *IRAM_ATTR wifi_zalloc_wrapper(size_t size)
|
||||
@ -91,14 +103,47 @@ wifi_static_queue_t *wifi_create_queue(int queue_len, int item_size)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
/* Wi-Fi still use internal RAM */
|
||||
|
||||
queue->storage = heap_caps_calloc(1, sizeof(StaticQueue_t) + (queue_len * item_size), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
||||
if (!queue->storage) {
|
||||
goto _error;
|
||||
}
|
||||
|
||||
queue->handle = xQueueCreateStatic(queue_len, item_size, ((uint8_t*)(queue->storage)) + sizeof(StaticQueue_t), (StaticQueue_t*)(queue->storage));
|
||||
|
||||
if (!queue->handle) {
|
||||
goto _error;
|
||||
}
|
||||
|
||||
return queue;
|
||||
|
||||
_error:
|
||||
if (queue) {
|
||||
if (queue->storage) {
|
||||
free(queue->storage);
|
||||
}
|
||||
|
||||
free(queue);
|
||||
}
|
||||
|
||||
return NULL;
|
||||
#else
|
||||
queue->handle = xQueueCreate(queue_len, item_size);
|
||||
return queue;
|
||||
#endif
|
||||
}
|
||||
|
||||
void wifi_delete_queue(wifi_static_queue_t *queue)
|
||||
{
|
||||
if (queue) {
|
||||
vQueueDelete(queue->handle);
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
if (queue->storage) {
|
||||
free(queue->storage);
|
||||
}
|
||||
#endif
|
||||
free(queue);
|
||||
}
|
||||
}
|
||||
@ -207,7 +252,32 @@ static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex)
|
||||
|
||||
static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
|
||||
{
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
StaticQueue_t *queue_buffer = heap_caps_malloc_prefer(sizeof(StaticQueue_t) + (queue_len * item_size), 2,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
if (!queue_buffer) {
|
||||
return NULL;
|
||||
}
|
||||
QueueHandle_t queue_handle = xQueueCreateStatic(queue_len, item_size, (uint8_t *)queue_buffer + sizeof(StaticQueue_t),
|
||||
queue_buffer);
|
||||
if (!queue_handle) {
|
||||
free(queue_buffer);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (void *)queue_handle;
|
||||
}
|
||||
|
||||
static void queue_delete_wrapper(void *queue)
|
||||
{
|
||||
if (queue) {
|
||||
StaticQueue_t *queue_buffer = NULL;
|
||||
xQueueGetStaticBuffers(queue, NULL, &queue_buffer);
|
||||
vQueueDelete(queue);
|
||||
if (queue_buffer) {
|
||||
free(queue_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int32_t queue_send_wrapper(void *queue, void *item, uint32_t block_time_tick)
|
||||
@ -587,7 +657,7 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
|
||||
._mutex_lock = mutex_lock_wrapper,
|
||||
._mutex_unlock = mutex_unlock_wrapper,
|
||||
._queue_create = queue_create_wrapper,
|
||||
._queue_delete = (void(*)(void *))vQueueDelete,
|
||||
._queue_delete = queue_delete_wrapper,
|
||||
._queue_send = queue_send_wrapper,
|
||||
._queue_send_from_isr = queue_send_from_isr_wrapper,
|
||||
._queue_send_to_back = queue_send_to_back_wrapper,
|
||||
|
758
components/esp_wifi/esp32c61/esp_adapter.c
Normal file
758
components/esp_wifi/esp32c61/esp_adapter.c
Normal file
@ -0,0 +1,758 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <pthread.h>
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "freertos/event_groups.h"
|
||||
#include "freertos/portmacro.h"
|
||||
#include "riscv/interrupt.h"
|
||||
#include "esp_types.h"
|
||||
#include "esp_random.h"
|
||||
#include "esp_mac.h"
|
||||
#include "esp_task.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_event.h"
|
||||
#include "esp_heap_caps.h"
|
||||
#include "esp_timer.h"
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
#include "esp_private/wifi_os_adapter.h"
|
||||
#include "esp_private/wifi.h"
|
||||
#ifdef CONFIG_ESP_PHY_ENABLED
|
||||
#include "esp_phy_init.h"
|
||||
#include "phy_init_data.h"
|
||||
#endif
|
||||
#include "soc/rtc_cntl_periph.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "esp_private/periph_ctrl.h"
|
||||
#include "esp_private/esp_clk.h"
|
||||
#include "nvs.h"
|
||||
#include "os.h"
|
||||
#include "esp_smartconfig.h"
|
||||
#ifdef CONFIG_ESP_COEX_ENABLED
|
||||
#include "private/esp_coexist_internal.h"
|
||||
#endif
|
||||
#include "esp32c61/rom/ets_sys.h"
|
||||
#include "private/esp_modem_wrapper.h"
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
|
||||
#if SOC_PM_MODEM_RETENTION_BY_REGDMA
|
||||
#include "esp_private/esp_regdma.h"
|
||||
#include "esp_private/sleep_retention.h"
|
||||
#endif
|
||||
|
||||
#define TAG "esp_adapter"
|
||||
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
extern void wifi_apb80m_request(void);
|
||||
extern void wifi_apb80m_release(void);
|
||||
#endif
|
||||
|
||||
IRAM_ATTR void *wifi_malloc(size_t size)
|
||||
{
|
||||
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
|
||||
return heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
#else
|
||||
return malloc(size);
|
||||
#endif
|
||||
}
|
||||
|
||||
IRAM_ATTR void *wifi_realloc(void *ptr, size_t size)
|
||||
{
|
||||
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
|
||||
return heap_caps_realloc_prefer(ptr, size, 2, MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
#else
|
||||
return realloc(ptr, size);
|
||||
#endif
|
||||
}
|
||||
|
||||
IRAM_ATTR void *wifi_calloc(size_t n, size_t size)
|
||||
{
|
||||
#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
|
||||
return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
#else
|
||||
return calloc(n, size);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void *IRAM_ATTR wifi_zalloc_wrapper(size_t size)
|
||||
{
|
||||
void *ptr = wifi_calloc(1, size);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
wifi_static_queue_t *wifi_create_queue(int queue_len, int item_size)
|
||||
{
|
||||
wifi_static_queue_t *queue = NULL;
|
||||
|
||||
queue = (wifi_static_queue_t *)heap_caps_malloc(sizeof(wifi_static_queue_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
||||
if (!queue) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
/* Wi-Fi still use internal RAM */
|
||||
|
||||
queue->storage = heap_caps_calloc(1, sizeof(StaticQueue_t) + (queue_len * item_size), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
||||
if (!queue->storage) {
|
||||
goto _error;
|
||||
}
|
||||
|
||||
queue->handle = xQueueCreateStatic(queue_len, item_size, ((uint8_t*)(queue->storage)) + sizeof(StaticQueue_t), (StaticQueue_t*)(queue->storage));
|
||||
|
||||
if (!queue->handle) {
|
||||
goto _error;
|
||||
}
|
||||
|
||||
return queue;
|
||||
|
||||
_error:
|
||||
if (queue) {
|
||||
if (queue->storage) {
|
||||
free(queue->storage);
|
||||
}
|
||||
|
||||
free(queue);
|
||||
}
|
||||
|
||||
return NULL;
|
||||
#else
|
||||
queue->handle = xQueueCreate(queue_len, item_size);
|
||||
return queue;
|
||||
#endif
|
||||
}
|
||||
|
||||
void wifi_delete_queue(wifi_static_queue_t *queue)
|
||||
{
|
||||
if (queue) {
|
||||
vQueueDelete(queue->handle);
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
if (queue->storage) {
|
||||
free(queue->storage);
|
||||
}
|
||||
#endif
|
||||
free(queue);
|
||||
}
|
||||
}
|
||||
|
||||
static void *wifi_create_queue_wrapper(int queue_len, int item_size)
|
||||
{
|
||||
return wifi_create_queue(queue_len, item_size);
|
||||
}
|
||||
|
||||
static void wifi_delete_queue_wrapper(void *queue)
|
||||
{
|
||||
wifi_delete_queue(queue);
|
||||
}
|
||||
|
||||
static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio)
|
||||
{
|
||||
esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num);
|
||||
esprv_int_set_priority(intr_num, intr_prio);
|
||||
esprv_int_set_type(intr_num, INTR_TYPE_LEVEL);
|
||||
}
|
||||
|
||||
static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static void set_isr_wrapper(int32_t n, void *f, void *arg)
|
||||
{
|
||||
intr_handler_set(n, (intr_handler_t)f, arg);
|
||||
}
|
||||
|
||||
static void enable_intr_wrapper(uint32_t intr_mask)
|
||||
{
|
||||
esprv_int_enable(intr_mask);
|
||||
}
|
||||
|
||||
static void disable_intr_wrapper(uint32_t intr_mask)
|
||||
{
|
||||
esprv_int_disable(intr_mask);
|
||||
}
|
||||
|
||||
static bool IRAM_ATTR is_from_isr_wrapper(void)
|
||||
{
|
||||
return !xPortCanYield();
|
||||
}
|
||||
|
||||
static void wifi_thread_semphr_free(void *data)
|
||||
{
|
||||
SemaphoreHandle_t *sem = (SemaphoreHandle_t *)(data);
|
||||
|
||||
if (sem) {
|
||||
vSemaphoreDelete(sem);
|
||||
}
|
||||
}
|
||||
|
||||
static void *wifi_thread_semphr_get_wrapper(void)
|
||||
{
|
||||
static bool s_wifi_thread_sem_key_init = false;
|
||||
static pthread_key_t s_wifi_thread_sem_key;
|
||||
SemaphoreHandle_t sem = NULL;
|
||||
|
||||
if (s_wifi_thread_sem_key_init == false) {
|
||||
if (0 != pthread_key_create(&s_wifi_thread_sem_key, wifi_thread_semphr_free)) {
|
||||
return NULL;
|
||||
}
|
||||
s_wifi_thread_sem_key_init = true;
|
||||
}
|
||||
|
||||
sem = pthread_getspecific(s_wifi_thread_sem_key);
|
||||
if (!sem) {
|
||||
sem = xSemaphoreCreateCounting(1, 0);
|
||||
if (sem) {
|
||||
pthread_setspecific(s_wifi_thread_sem_key, sem);
|
||||
ESP_LOGV(TAG, "thread sem create: sem=%p", sem);
|
||||
}
|
||||
}
|
||||
|
||||
ESP_LOGV(TAG, "thread sem get: sem=%p", sem);
|
||||
return (void *)sem;
|
||||
}
|
||||
|
||||
static void *recursive_mutex_create_wrapper(void)
|
||||
{
|
||||
return (void *)xSemaphoreCreateRecursiveMutex();
|
||||
}
|
||||
|
||||
static void *mutex_create_wrapper(void)
|
||||
{
|
||||
return (void *)xSemaphoreCreateMutex();
|
||||
}
|
||||
|
||||
static void mutex_delete_wrapper(void *mutex)
|
||||
{
|
||||
vSemaphoreDelete(mutex);
|
||||
}
|
||||
|
||||
static int32_t IRAM_ATTR mutex_lock_wrapper(void *mutex)
|
||||
{
|
||||
return (int32_t)xSemaphoreTakeRecursive(mutex, portMAX_DELAY);
|
||||
}
|
||||
|
||||
static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex)
|
||||
{
|
||||
return (int32_t)xSemaphoreGiveRecursive(mutex);
|
||||
}
|
||||
|
||||
static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
|
||||
{
|
||||
StaticQueue_t *queue_buffer = heap_caps_malloc_prefer(sizeof(StaticQueue_t) + (queue_len * item_size), 2,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
if (!queue_buffer) {
|
||||
return NULL;
|
||||
}
|
||||
QueueHandle_t queue_handle = xQueueCreateStatic(queue_len, item_size, (uint8_t *)queue_buffer + sizeof(StaticQueue_t),
|
||||
queue_buffer);
|
||||
if (!queue_handle) {
|
||||
free(queue_buffer);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (void *)queue_handle;
|
||||
}
|
||||
|
||||
static void queue_delete_wrapper(void *queue)
|
||||
{
|
||||
if (queue) {
|
||||
StaticQueue_t *queue_buffer = NULL;
|
||||
xQueueGetStaticBuffers(queue, NULL, &queue_buffer);
|
||||
vQueueDelete(queue);
|
||||
if (queue_buffer) {
|
||||
free(queue_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int32_t queue_send_wrapper(void *queue, void *item, uint32_t block_time_tick)
|
||||
{
|
||||
if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) {
|
||||
return (int32_t)xQueueSend(queue, item, portMAX_DELAY);
|
||||
} else {
|
||||
return (int32_t)xQueueSend(queue, item, block_time_tick);
|
||||
}
|
||||
}
|
||||
|
||||
static int32_t IRAM_ATTR queue_send_from_isr_wrapper(void *queue, void *item, void *hptw)
|
||||
{
|
||||
return (int32_t)xQueueSendFromISR(queue, item, hptw);
|
||||
}
|
||||
|
||||
static int32_t queue_send_to_back_wrapper(void *queue, void *item, uint32_t block_time_tick)
|
||||
{
|
||||
return (int32_t)xQueueGenericSend(queue, item, block_time_tick, queueSEND_TO_BACK);
|
||||
}
|
||||
|
||||
static int32_t queue_send_to_front_wrapper(void *queue, void *item, uint32_t block_time_tick)
|
||||
{
|
||||
return (int32_t)xQueueGenericSend(queue, item, block_time_tick, queueSEND_TO_FRONT);
|
||||
}
|
||||
|
||||
static int32_t queue_recv_wrapper(void *queue, void *item, uint32_t block_time_tick)
|
||||
{
|
||||
if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) {
|
||||
return (int32_t)xQueueReceive(queue, item, portMAX_DELAY);
|
||||
} else {
|
||||
return (int32_t)xQueueReceive(queue, item, block_time_tick);
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t event_group_wait_bits_wrapper(void *event, uint32_t bits_to_wait_for, int clear_on_exit, int wait_for_all_bits, uint32_t block_time_tick)
|
||||
{
|
||||
if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) {
|
||||
return (uint32_t)xEventGroupWaitBits(event, bits_to_wait_for, clear_on_exit, wait_for_all_bits, portMAX_DELAY);
|
||||
} else {
|
||||
return (uint32_t)xEventGroupWaitBits(event, bits_to_wait_for, clear_on_exit, wait_for_all_bits, block_time_tick);
|
||||
}
|
||||
}
|
||||
|
||||
static int32_t task_create_pinned_to_core_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id)
|
||||
{
|
||||
return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle, (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY));
|
||||
}
|
||||
|
||||
static int32_t task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle)
|
||||
{
|
||||
return (uint32_t)xTaskCreate(task_func, name, stack_depth, param, prio, task_handle);
|
||||
}
|
||||
|
||||
static int32_t IRAM_ATTR task_ms_to_tick_wrapper(uint32_t ms)
|
||||
{
|
||||
return (int32_t)(ms / portTICK_PERIOD_MS);
|
||||
}
|
||||
|
||||
static int32_t task_get_max_priority_wrapper(void)
|
||||
{
|
||||
return (int32_t)(configMAX_PRIORITIES);
|
||||
}
|
||||
|
||||
static int32_t esp_event_post_wrapper(const char *event_base, int32_t event_id, void *event_data, size_t event_data_size, uint32_t ticks_to_wait)
|
||||
{
|
||||
if (ticks_to_wait == OSI_FUNCS_TIME_BLOCKING) {
|
||||
return (int32_t)esp_event_post(event_base, event_id, event_data, event_data_size, portMAX_DELAY);
|
||||
} else {
|
||||
return (int32_t)esp_event_post(event_base, event_id, event_data, event_data_size, ticks_to_wait);
|
||||
}
|
||||
}
|
||||
|
||||
static void IRAM_ATTR wifi_apb80m_request_wrapper(void)
|
||||
{
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
wifi_apb80m_request();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void IRAM_ATTR wifi_apb80m_release_wrapper(void)
|
||||
{
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
wifi_apb80m_release();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void IRAM_ATTR timer_arm_wrapper(void *timer, uint32_t tmout, bool repeat)
|
||||
{
|
||||
ets_timer_arm(timer, tmout, repeat);
|
||||
}
|
||||
|
||||
static void wifi_reset_mac_wrapper(void)
|
||||
{
|
||||
modem_clock_module_mac_reset(PERIPH_WIFI_MODULE);
|
||||
}
|
||||
|
||||
static void wifi_clock_enable_wrapper(void)
|
||||
{
|
||||
wifi_module_enable();
|
||||
}
|
||||
|
||||
static void wifi_clock_disable_wrapper(void)
|
||||
{
|
||||
wifi_module_disable();
|
||||
}
|
||||
|
||||
static int get_time_wrapper(void *t)
|
||||
{
|
||||
return os_get_time(t);
|
||||
}
|
||||
|
||||
static void *IRAM_ATTR realloc_internal_wrapper(void *ptr, size_t size)
|
||||
{
|
||||
return heap_caps_realloc(ptr, size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
|
||||
}
|
||||
|
||||
static void *IRAM_ATTR calloc_internal_wrapper(size_t n, size_t size)
|
||||
{
|
||||
return heap_caps_calloc(n, size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
|
||||
}
|
||||
|
||||
static void *IRAM_ATTR zalloc_internal_wrapper(size_t size)
|
||||
{
|
||||
void *ptr = heap_caps_calloc(1, size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
static esp_err_t nvs_open_wrapper(const char *name, unsigned int open_mode, nvs_handle_t *out_handle)
|
||||
{
|
||||
return nvs_open(name, (nvs_open_mode_t)open_mode, out_handle);
|
||||
}
|
||||
|
||||
static void esp_log_writev_wrapper(unsigned int level, const char *tag, const char *format, va_list args)
|
||||
{
|
||||
return esp_log_writev((esp_log_level_t)level, tag, format, args);
|
||||
}
|
||||
|
||||
static void esp_log_write_wrapper(unsigned int level, const char *tag, const char *format, ...)
|
||||
{
|
||||
va_list list;
|
||||
va_start(list, format);
|
||||
esp_log_writev((esp_log_level_t)level, tag, format, list);
|
||||
va_end(list);
|
||||
}
|
||||
|
||||
static esp_err_t esp_read_mac_wrapper(uint8_t *mac, unsigned int type)
|
||||
{
|
||||
return esp_read_mac(mac, (esp_mac_type_t)type);
|
||||
}
|
||||
|
||||
static int coex_init_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_init();
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void coex_deinit_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
coex_deinit();
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_enable_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_enable();
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void coex_disable_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
coex_disable();
|
||||
#endif
|
||||
}
|
||||
|
||||
static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_status_get();
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_wifi_request_wrapper(uint32_t event, uint32_t latency, uint32_t duration)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_wifi_request(event, latency, duration);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static IRAM_ATTR int coex_wifi_release_wrapper(uint32_t event)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_wifi_release(event);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_wifi_channel_set_wrapper(uint8_t primary, uint8_t secondary)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_wifi_channel_set(primary, secondary);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static IRAM_ATTR int coex_event_duration_get_wrapper(uint32_t event, uint32_t *duration)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_event_duration_get(event, duration);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_pti_get(event, pti);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
coex_schm_status_bit_clear(type, status);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
coex_schm_status_bit_set(type, status);
|
||||
#endif
|
||||
}
|
||||
|
||||
static IRAM_ATTR int coex_schm_interval_set_wrapper(uint32_t interval)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_schm_interval_set(interval);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static uint32_t coex_schm_interval_get_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_schm_interval_get();
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static uint8_t coex_schm_curr_period_get_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_schm_curr_period_get();
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void *coex_schm_curr_phase_get_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
|
||||
return coex_schm_curr_phase_get();
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_register_start_cb_wrapper(int (* cb)(void))
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE
|
||||
return coex_register_start_cb(cb);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_schm_process_restart_wrapper(void)
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE
|
||||
return coex_schm_process_restart();
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_schm_register_cb_wrapper(int type, int(*cb)(int))
|
||||
{
|
||||
#if CONFIG_SW_COEXIST_ENABLE
|
||||
return coex_schm_register_callback(type, cb);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int coex_schm_flexible_period_set_wrapper(uint8_t period)
|
||||
{
|
||||
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
|
||||
return coex_schm_flexible_period_set(period);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static uint8_t coex_schm_flexible_period_get_wrapper(void)
|
||||
{
|
||||
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
|
||||
return coex_schm_flexible_period_get();
|
||||
#else
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void IRAM_ATTR esp_empty_wrapper(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
extern void set_bb_wdg(bool busy_chk, bool srch_chk, uint16_t max_busy, uint16_t max_srch, bool rst_en, bool int_en, bool clr);
|
||||
|
||||
static void esp_phy_enable_wrapper(void)
|
||||
{
|
||||
esp_phy_enable(PHY_MODEM_WIFI);
|
||||
phy_wifi_enable_set(1);
|
||||
//disable bb idle check(max: 139ms) for temporary to avoid unexpected RXTXPANIC
|
||||
//TODO
|
||||
set_bb_wdg(true, false, 0x18, 0xaa, false, false, false);
|
||||
}
|
||||
|
||||
static void esp_phy_disable_wrapper(void)
|
||||
{
|
||||
phy_wifi_enable_set(0);
|
||||
esp_phy_disable(PHY_MODEM_WIFI);
|
||||
}
|
||||
|
||||
wifi_osi_funcs_t g_wifi_osi_funcs = {
|
||||
._version = ESP_WIFI_OS_ADAPTER_VERSION,
|
||||
._env_is_chip = esp_coex_common_env_is_chip_wrapper,
|
||||
._set_intr = set_intr_wrapper,
|
||||
._clear_intr = clear_intr_wrapper,
|
||||
._set_isr = set_isr_wrapper,
|
||||
._ints_on = enable_intr_wrapper,
|
||||
._ints_off = disable_intr_wrapper,
|
||||
._is_from_isr = is_from_isr_wrapper,
|
||||
._spin_lock_create = esp_coex_common_spin_lock_create_wrapper,
|
||||
._spin_lock_delete = free,
|
||||
._wifi_int_disable = esp_coex_common_int_disable_wrapper,
|
||||
._wifi_int_restore = esp_coex_common_int_restore_wrapper,
|
||||
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
|
||||
._semphr_create = esp_coex_common_semphr_create_wrapper,
|
||||
._semphr_delete = esp_coex_common_semphr_delete_wrapper,
|
||||
._semphr_take = esp_coex_common_semphr_take_wrapper,
|
||||
._semphr_give = esp_coex_common_semphr_give_wrapper,
|
||||
._wifi_thread_semphr_get = wifi_thread_semphr_get_wrapper,
|
||||
._mutex_create = mutex_create_wrapper,
|
||||
._recursive_mutex_create = recursive_mutex_create_wrapper,
|
||||
._mutex_delete = mutex_delete_wrapper,
|
||||
._mutex_lock = mutex_lock_wrapper,
|
||||
._mutex_unlock = mutex_unlock_wrapper,
|
||||
._queue_create = queue_create_wrapper,
|
||||
._queue_delete = queue_delete_wrapper,
|
||||
._queue_send = queue_send_wrapper,
|
||||
._queue_send_from_isr = queue_send_from_isr_wrapper,
|
||||
._queue_send_to_back = queue_send_to_back_wrapper,
|
||||
._queue_send_to_front = queue_send_to_front_wrapper,
|
||||
._queue_recv = queue_recv_wrapper,
|
||||
._queue_msg_waiting = (uint32_t(*)(void *))uxQueueMessagesWaiting,
|
||||
._event_group_create = (void *(*)(void))xEventGroupCreate,
|
||||
._event_group_delete = (void(*)(void *))vEventGroupDelete,
|
||||
._event_group_set_bits = (uint32_t(*)(void *, uint32_t))xEventGroupSetBits,
|
||||
._event_group_clear_bits = (uint32_t(*)(void *, uint32_t))xEventGroupClearBits,
|
||||
._event_group_wait_bits = event_group_wait_bits_wrapper,
|
||||
._task_create_pinned_to_core = task_create_pinned_to_core_wrapper,
|
||||
._task_create = task_create_wrapper,
|
||||
._task_delete = (void(*)(void *))vTaskDelete,
|
||||
._task_delay = vTaskDelay,
|
||||
._task_ms_to_tick = task_ms_to_tick_wrapper,
|
||||
._task_get_current_task = (void *(*)(void))xTaskGetCurrentTaskHandle,
|
||||
._task_get_max_priority = task_get_max_priority_wrapper,
|
||||
._malloc = malloc,
|
||||
._free = free,
|
||||
._event_post = esp_event_post_wrapper,
|
||||
._get_free_heap_size = esp_get_free_internal_heap_size,
|
||||
._rand = esp_random,
|
||||
._dport_access_stall_other_cpu_start_wrap = esp_empty_wrapper,
|
||||
._dport_access_stall_other_cpu_end_wrap = esp_empty_wrapper,
|
||||
._wifi_apb80m_request = wifi_apb80m_request_wrapper,
|
||||
._wifi_apb80m_release = wifi_apb80m_release_wrapper,
|
||||
._phy_disable = esp_phy_disable_wrapper,
|
||||
._phy_enable = esp_phy_enable_wrapper,
|
||||
._phy_update_country_info = esp_phy_update_country_info,
|
||||
._read_mac = esp_read_mac_wrapper,
|
||||
._timer_arm = timer_arm_wrapper,
|
||||
._timer_disarm = esp_coex_common_timer_disarm_wrapper,
|
||||
._timer_done = esp_coex_common_timer_done_wrapper,
|
||||
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
|
||||
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
|
||||
._wifi_reset_mac = wifi_reset_mac_wrapper,
|
||||
._wifi_clock_enable = wifi_clock_enable_wrapper,
|
||||
._wifi_clock_disable = wifi_clock_disable_wrapper,
|
||||
._wifi_rtc_enable_iso = esp_empty_wrapper,
|
||||
._wifi_rtc_disable_iso = esp_empty_wrapper,
|
||||
._esp_timer_get_time = esp_timer_get_time,
|
||||
._nvs_set_i8 = nvs_set_i8,
|
||||
._nvs_get_i8 = nvs_get_i8,
|
||||
._nvs_set_u8 = nvs_set_u8,
|
||||
._nvs_get_u8 = nvs_get_u8,
|
||||
._nvs_set_u16 = nvs_set_u16,
|
||||
._nvs_get_u16 = nvs_get_u16,
|
||||
._nvs_open = nvs_open_wrapper,
|
||||
._nvs_close = nvs_close,
|
||||
._nvs_commit = nvs_commit,
|
||||
._nvs_set_blob = nvs_set_blob,
|
||||
._nvs_get_blob = nvs_get_blob,
|
||||
._nvs_erase_key = nvs_erase_key,
|
||||
._get_random = os_get_random,
|
||||
._get_time = get_time_wrapper,
|
||||
._random = os_random,
|
||||
._slowclk_cal_get = esp_coex_common_clk_slowclk_cal_get_wrapper,
|
||||
._log_write = esp_log_write_wrapper,
|
||||
._log_writev = esp_log_writev_wrapper,
|
||||
._log_timestamp = esp_log_timestamp,
|
||||
._malloc_internal = esp_coex_common_malloc_internal_wrapper,
|
||||
._realloc_internal = realloc_internal_wrapper,
|
||||
._calloc_internal = calloc_internal_wrapper,
|
||||
._zalloc_internal = zalloc_internal_wrapper,
|
||||
._wifi_malloc = wifi_malloc,
|
||||
._wifi_realloc = wifi_realloc,
|
||||
._wifi_calloc = wifi_calloc,
|
||||
._wifi_zalloc = wifi_zalloc_wrapper,
|
||||
._wifi_create_queue = wifi_create_queue_wrapper,
|
||||
._wifi_delete_queue = wifi_delete_queue_wrapper,
|
||||
._coex_init = coex_init_wrapper,
|
||||
._coex_deinit = coex_deinit_wrapper,
|
||||
._coex_enable = coex_enable_wrapper,
|
||||
._coex_disable = coex_disable_wrapper,
|
||||
._coex_status_get = coex_status_get_wrapper,
|
||||
._coex_wifi_request = coex_wifi_request_wrapper,
|
||||
._coex_wifi_release = coex_wifi_release_wrapper,
|
||||
._coex_wifi_channel_set = coex_wifi_channel_set_wrapper,
|
||||
._coex_event_duration_get = coex_event_duration_get_wrapper,
|
||||
._coex_pti_get = coex_pti_get_wrapper,
|
||||
._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
|
||||
._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
|
||||
._coex_schm_interval_set = coex_schm_interval_set_wrapper,
|
||||
._coex_schm_interval_get = coex_schm_interval_get_wrapper,
|
||||
._coex_schm_curr_period_get = coex_schm_curr_period_get_wrapper,
|
||||
._coex_schm_curr_phase_get = coex_schm_curr_phase_get_wrapper,
|
||||
._coex_register_start_cb = coex_register_start_cb_wrapper,
|
||||
#if SOC_PM_MODEM_RETENTION_BY_REGDMA
|
||||
._regdma_link_set_write_wait_content = regdma_link_set_write_wait_content,
|
||||
._sleep_retention_find_link_by_id = sleep_retention_find_link_by_id,
|
||||
#endif
|
||||
._coex_schm_process_restart = coex_schm_process_restart_wrapper,
|
||||
._coex_schm_register_cb = coex_schm_register_cb_wrapper,
|
||||
._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
|
||||
._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
|
||||
._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
|
||||
};
|
@ -257,7 +257,32 @@ static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex)
|
||||
|
||||
static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
|
||||
{
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
StaticQueue_t *queue_buffer = heap_caps_malloc_prefer(sizeof(StaticQueue_t) + (queue_len * item_size), 2,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
if (!queue_buffer) {
|
||||
return NULL;
|
||||
}
|
||||
QueueHandle_t queue_handle = xQueueCreateStatic(queue_len, item_size, (uint8_t *)queue_buffer + sizeof(StaticQueue_t),
|
||||
queue_buffer);
|
||||
if (!queue_handle) {
|
||||
free(queue_buffer);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (void *)queue_handle;
|
||||
}
|
||||
|
||||
static void queue_delete_wrapper(void *queue)
|
||||
{
|
||||
if (queue) {
|
||||
StaticQueue_t *queue_buffer = NULL;
|
||||
xQueueGetStaticBuffers(queue, NULL, &queue_buffer);
|
||||
vQueueDelete(queue);
|
||||
if (queue_buffer) {
|
||||
free(queue_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int32_t queue_send_wrapper(void *queue, void *item, uint32_t block_time_tick)
|
||||
@ -691,7 +716,7 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
|
||||
._mutex_lock = mutex_lock_wrapper,
|
||||
._mutex_unlock = mutex_unlock_wrapper,
|
||||
._queue_create = queue_create_wrapper,
|
||||
._queue_delete = (void(*)(void *))vQueueDelete,
|
||||
._queue_delete = queue_delete_wrapper,
|
||||
._queue_send = queue_send_wrapper,
|
||||
._queue_send_from_isr = queue_send_from_isr_wrapper,
|
||||
._queue_send_to_back = queue_send_to_back_wrapper,
|
||||
|
@ -50,6 +50,9 @@
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#include "private/esp_modem_wrapper.h"
|
||||
#if __has_include("esp_psram.h")
|
||||
#include "esp_psram.h"
|
||||
#endif
|
||||
|
||||
#define TAG "esp_adapter"
|
||||
|
||||
@ -251,36 +254,31 @@ static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex)
|
||||
|
||||
static void * queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
|
||||
{
|
||||
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
|
||||
/*
|
||||
* Since release/v5.1, FreeRTOS has been updated to always use internal memory (i.e., DRAM)
|
||||
* for dynamic memory allocation. Calling FreeRTOS creation functions (e.g., xTaskCreate(), xQueueCreate())
|
||||
* will guarantee that the memory allocated for those tasks/objects is from internal memory.
|
||||
* For more details, please refer to the Migration Guide in release/v5.1.
|
||||
*/
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
/* Use xQueueCreateWithCaps() to allocate from SPIRAM */
|
||||
return (void *)xQueueCreateWithCaps(queue_len, item_size, MALLOC_CAP_SPIRAM);
|
||||
#else
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
#endif
|
||||
#else
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
#endif
|
||||
StaticQueue_t *queue_buffer = heap_caps_malloc_prefer(sizeof(StaticQueue_t) + (queue_len * item_size), 2,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
if (!queue_buffer) {
|
||||
return NULL;
|
||||
}
|
||||
QueueHandle_t queue_handle = xQueueCreateStatic(queue_len, item_size, (uint8_t *)queue_buffer + sizeof(StaticQueue_t),
|
||||
queue_buffer);
|
||||
if (!queue_handle) {
|
||||
free(queue_buffer);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (void *)queue_handle;
|
||||
}
|
||||
|
||||
static void queue_delete_wrapper(void *queue)
|
||||
{
|
||||
if (queue) {
|
||||
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
vQueueDeleteWithCaps(queue);
|
||||
#else
|
||||
StaticQueue_t *queue_buffer = NULL;
|
||||
xQueueGetStaticBuffers(queue, NULL, &queue_buffer);
|
||||
vQueueDelete(queue);
|
||||
#endif
|
||||
#else
|
||||
vQueueDelete(queue);
|
||||
#endif
|
||||
if (queue_buffer) {
|
||||
free(queue_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -51,6 +51,9 @@
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp32s3/rom/ets_sys.h"
|
||||
#include "private/esp_modem_wrapper.h"
|
||||
#if __has_include("esp_psram.h")
|
||||
#include "esp_psram.h"
|
||||
#endif
|
||||
|
||||
#define TAG "esp_adapter"
|
||||
|
||||
@ -254,36 +257,31 @@ static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex)
|
||||
|
||||
static void * queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
|
||||
{
|
||||
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
|
||||
/*
|
||||
* Since release/v5.1, FreeRTOS has been updated to always use internal memory (i.e., DRAM)
|
||||
* for dynamic memory allocation. Calling FreeRTOS creation functions (e.g., xTaskCreate(), xQueueCreate())
|
||||
* will guarantee that the memory allocated for those tasks/objects is from internal memory.
|
||||
* For more details, please refer to the Migration Guide in release/v5.1.
|
||||
*/
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
/* Use xQueueCreateWithCaps() to allocate from SPIRAM */
|
||||
return (void *)xQueueCreateWithCaps(queue_len, item_size, MALLOC_CAP_SPIRAM);
|
||||
#else
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
#endif
|
||||
#else
|
||||
return (void *)xQueueCreate(queue_len, item_size);
|
||||
#endif
|
||||
StaticQueue_t *queue_buffer = heap_caps_malloc_prefer(sizeof(StaticQueue_t) + (queue_len * item_size), 2,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_SPIRAM,
|
||||
MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL);
|
||||
if (!queue_buffer) {
|
||||
return NULL;
|
||||
}
|
||||
QueueHandle_t queue_handle = xQueueCreateStatic(queue_len, item_size, (uint8_t *)queue_buffer + sizeof(StaticQueue_t),
|
||||
queue_buffer);
|
||||
if (!queue_handle) {
|
||||
free(queue_buffer);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (void *)queue_handle;
|
||||
}
|
||||
|
||||
static void queue_delete_wrapper(void *queue)
|
||||
{
|
||||
if (queue) {
|
||||
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
|
||||
#if CONFIG_SPIRAM_USE_MALLOC
|
||||
vQueueDeleteWithCaps(queue);
|
||||
#else
|
||||
StaticQueue_t *queue_buffer = NULL;
|
||||
xQueueGetStaticBuffers(queue, NULL, &queue_buffer);
|
||||
vQueueDelete(queue);
|
||||
#endif
|
||||
#else
|
||||
vQueueDelete(queue);
|
||||
#endif
|
||||
if (queue_buffer) {
|
||||
free(queue_buffer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -189,7 +189,7 @@ typedef struct {
|
||||
uint32_t txbf;
|
||||
uint32_t dcm;
|
||||
} nonmimo[ESP_TEST_RX_MU_USER_NUM];
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
|
||||
uint32_t mu_bru_id_0: 16;
|
||||
uint32_t mu_bru_id_bssidx: 16;
|
||||
uint32_t mu_bru_id_2047: 16;
|
||||
@ -200,7 +200,7 @@ typedef struct {
|
||||
#endif
|
||||
} esp_test_rx_mu_statistics_t; //10932 bytes
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
|
||||
typedef struct {
|
||||
uint32_t legacy;
|
||||
uint32_t legacy_noeb;
|
||||
@ -406,7 +406,7 @@ typedef struct {
|
||||
uint16_t rxhung_statis;
|
||||
uint16_t txhung_statis;
|
||||
uint32_t rxtxhung;
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
|
||||
uint32_t rxtxpanic;
|
||||
uint8_t bf_ndp_timeout;
|
||||
uint8_t bf_report_err;
|
||||
|
@ -149,7 +149,7 @@ typedef struct wifi_osi_funcs_t {
|
||||
int (* _coex_schm_process_restart)(void);
|
||||
int (* _coex_schm_register_cb)(int, int (* cb)(int));
|
||||
int (* _coex_register_start_cb)(int (* cb)(void));
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
|
||||
void (* _regdma_link_set_write_wait_content)(void *, uint32_t, uint32_t);
|
||||
void * (* _sleep_retention_find_link_by_id)(int);
|
||||
#endif
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
@ -41,7 +41,7 @@ enum {
|
||||
/**
|
||||
* @brief Channel state information(CSI) configuration type
|
||||
*/
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
|
||||
typedef struct {
|
||||
uint32_t enable : 1; /**< enable to acquire CSI */
|
||||
uint32_t acquire_csi_legacy : 1; /**< enable to acquire L-LTF */
|
||||
@ -172,7 +172,7 @@ typedef enum {
|
||||
/**
|
||||
* @brief RxControl Info
|
||||
*/
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
|
||||
typedef struct {
|
||||
signed rssi: 8; /**< the RSSI of the reception frame */
|
||||
unsigned rate: 5; /**< if cur_bb_format is RX_BB_FORMAT_11B, it's the transmission rate. otherwise it's Rate field of L-SIG */
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user