portBASE_TYPE is an internal macro defined by the porting layer. This commit
changes all references to BaseType_t which is the official type exposed by
FreeRTOS.
The caches are disabled when reading/writing/erasing flash.
All CPUs should always execute code and access data from internal RAM.
Add an IRAM option to enhance the performance of LEDC.
Closes https://github.com/espressif/esp-idf/issues/11554
1. Regression introduced when refactoring on clock sources selection (0d07f859).
If channel configuration is called before timer configuration on C6, PWM signal may not be able to output.
2. Missing the improper fade parameter fix inside ledc_set_duty_and_update() function.
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2