5 Commits

Author	SHA1	Message	Date
Li Shuai	1a10eabe41	Power Management: refactor the configuration of each module in sleep mode	2023-03-04 00:17:40 +08:00
wuzhenghui	9eae151f7c	esp32c6: bringup deepsleep examples	2023-03-02 15:06:05 +08:00
Armando	4997689de5	cache: support h2 and c6 cache error	2023-02-24 16:16:46 +08:00
Li Shuai	9b99fc9033	cpu retention: software cpu retention support for esp32c6 ... cpu retention: add riscv core sleep critical and non-critical register layout structure definition cpu retention: add assembly subroutine for cpu critical register backup and restore cpu retention: add cpu core critical register context backup and restore support cpu retention: add cpu core non-critical register context backup and restore support cpu retention: add interrupt priority register context backup and restore support cpu retention: add cache config register context backup and restore support cpu retention: add plic interrupt register context backup and restore support cpu retention: add clint interrupt register context backup and restore support cpu retention: wait icache state idle before pmu enter sleep	2023-01-31 22:12:54 +08:00
Li Shuai	1c39d64f95	cpu retention: refactor cpu retention and add cpu retention versions option in soc caps	2023-01-31 22:12:50 +08:00