alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity
19,462 Commits 20 Branches 148 Tags 384 MiB
f57d0fcc5e
Commit Graph

26 Commits

Author SHA1 Message Date
Otto Winter
381ac08f12 bugfix (esp_common): remove infinite recursion in FLAG_ATTR operator 
Closes https://github.com/espressif/esp-idf/pull/7754

Signed-off-by: Jakob Hasse <jakob.hasse@espressif.com>
 2023-04-17 18:37:15 +08:00
Omar Chebib
e1d3993309 RISC-V: Fix vectors.S assembly file indentation and macro usage 
The file is now more consistent as the macros have been fixed, more comments
have been added and the indentation is now using spaces only.
 2022-04-22 13:17:59 +03:00
Alexey Gerenkov
dfd3a9c3bc riscv: Use semihosting to set breakpoint and watchpoint when running under debugger 2022-04-22 13:17:54 +03:00
Alexey Gerenkov
4edc903bb3 riscv: Adds support for returning from exception handler 2022-04-22 12:38:16 +03:00
Alexey Gerenkov
f8a0279e5d riscv: Fixes GDB backtrace of interrupted threads 
Save missed SP value on stack
 2022-04-22 12:38:16 +03:00
Omar Chebib
824552e9b4 RISC-V: fix usage of special register when interrupts are enabled 2021-12-21 01:06:11 +00:00
Renz Bagaporo
5f2fabb2b1 arch: move stdatomic 2021-11-02 16:24:18 +01:00
Marius Vikhammer
57442c38bd core: fix cases where riscv SP were not 16 byte aligned 
RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
 2021-06-02 16:02:10 +08:00
Sachin Parekh
aad1f7abde stdatomic: Implemented legacy __sync APIs and __atomic_exchange_n 
These APIs are used when the architecture doesn't have atomic
instruction support

Closes https://github.com/espressif/esp-idf/issues/6463
 2021-04-27 13:34:54 +05:30
Marius Vikhammer
360e7c4d51 system: enable shared stack watchpoint 
Enable shared stack watchpoint for overflow detection

Enable unit tests:
 * "test printf using shared buffer stack" for C3
 * "Test vTaskDelayUntil" for S2
 * "UART can do poll()" for C3
 2021-02-19 16:59:29 +08:00
Martin Vychodil
69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0) 
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
 2021-01-27 08:44:03 +01:00
Li Shuai
355dd10257 light sleep: dfs support for esp32c3 2021-01-19 14:50:58 +08:00
Jakob Hasse
b51889dccb system: stack watchpoint support on C3 
Closes IDF-2307
 2021-01-14 17:46:44 +08:00
morris
7a71cedf87 interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
morris
9e7d2c0065 esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
Felipe Neves
72e4655d4e interrupt: removed descriptor table from esp32c3 interrupt hal. 2021-01-05 15:39:46 +08:00
Felipe Neves
544a3f7df5 interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available 2021-01-05 15:39:46 +08:00
Felipe Neves
ec5acf91ee esp_shared_stack: enable shared stack function for riscv and reenable the unit test 2021-01-05 15:39:46 +08:00
Felipe Neves
f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Felipe Neves
810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. 
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
 2021-01-05 15:39:46 +08:00
Omar Chebib
c218f669ba panic on RISC-V: Take into account Merge Request comments 2020-12-31 15:46:17 +08:00
Omar Chebib
a90dcfba1a panic: Add support for SoC-level panic 
Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
 2020-12-31 15:46:17 +08:00
Omar Chebib
b6a450f824 panic: Add support for SoC-level panic 
SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
 2020-12-31 15:46:17 +08:00
Angus Gratton
e2d4f0e320 riscv: Place stdatomic file in iram 2020-12-24 14:18:01 +11:00
Renz Bagaporo
4cc6b5571b esp_system: support riscv panic 2020-11-13 07:49:11 +11:00
Angus Gratton
fccab8f4ef riscv: Add new arch-level component 
Changes come from internal branch commit a6723fc
 2020-11-12 09:33:18 +11:00