This commit fixes an issue where in the FreeRTOS port layer would cause
the portASSERT_IF_IN_ISR() assert check to fail even when the system is
not in an interrupt context.
FreeRTOS tasks may now freely use the PIE coprocessor and HWLP feature.
Just like the FPU, usiing these coprocessors result in the task being pinned
to the core it is currently running on.
vTaskSuspendAll() requires critical sections when building for SMP. Otherwise,
it is possible for a task to switch cores in between getting the core ID and
before incremented uxSchedulerSuspended.
xCoreID was previously printed as the last parameter priority to IDF v5.1, but
was changed to the third paramtere from v5.2 onwards. This commit restores the
correct ordering.
Closes https://github.com/espressif/esp-idf/issues/13675
This commit fixes a bug where the portTRY_ENTER_CRITICAL_SAFE() for the
Xtensa and RISC-V FreeRTOS ports were broken as it did not correctly use
the timeout parameter.
Merges: https://github.com/espressif/esp-idf/pull/13022
- move .tbss to NOLOAD section
- remove xtensa-specific entities from riscv scripts
- explicit eh_frame terminator instead of "align magic"
- 80 characters line length limit
- refactor comments
- discard .rela sections (the rela data will go to relates sections)
fix(riscv): Updated RISC-V functions to set interrupt threshold for CLIC targets
Closes IDFCI-2033, IDFCI-2034, IDF-8090, and IDF-8117
See merge request espressif/esp-idf!29055
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:
- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data
If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):
.dram0.bss (NOLOAD) :
{
arrays[dram0_bss]
mapping[dram0_bss]
} > sram_low
.dram1.bss (NOLOAD) :
{
/* do not place here arrays[dram0_bss] because it may be splited
* between segments */
mapping[dram0_bss]
} > sram_high
This commit added the RISC-V utility functions to set the interrupt
threshold for CLIC targets by using direct register value writes.
This makes the functions more efficient during run-time.
This is done to improve the critical section enter and exit performance on esp32p4.
This commit does the following:
- removes the xCoreID member from the TCB when building for single-core
- xCoreID is no longer hard set to 0 when calling "PinnedToCore" task creation
functions in single-core
- Tidy up or add missing xCoreID asserts for functions that take xCoreID as an
argument:
- Functions that set/query a variable of a particular core will call
taskVALID_CORE_ID() to ensure ) 0 <= xCoreID < configNUMBER_OF_CORES
- Task creation functions that accept xCoreID also call taskVALID_CORE_ID()
but also allow tskNO_AFFINITY.
- Fix TaskStatus_t
- Remove xCoreID from TaskStatus_t if configTASKLIST_INCLUDE_COREID is not
defined.
- Set xCoreID to 0 when calling vTaskGetInfo() in single-core builds
This commit refactors the following macros so that calling them no longer
requires referencing pxTCB->xCoreID.
- taskIS_YIELD_REQUIRED()
- taskIS_YIELD_REQUIRED_USING_PRIORITY()
- taskIS_AFFINITY_COMPATIBLE()
This commit deprecates the "freertos/xtensa_context.h" and "xtensa/xtensa_context.h"
include paths. Users should use "xtensa_context.h" instead.
- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Add warning to compatibility header
This commit deprecates the "freertos/xtensa_api.h" and "xtensa/xtensa_api.h"
include paths. Users should use "xtensa_api.h" instead.
- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Replaced some calls with "esp_cpu_..." equivalents
- Add warning to compatibility header
This commit adds the ability to set the core affinity for the FreeRTOS
Timer Service task when multi-core configuration is enabled. This commit
also adds a Kconfig option to set the core affinity of the timer task
via the menuconfig.
Closes https://github.com/espressif/esp-idf/issues/10315
This commit adds a taskVALID_CORE_ID() macro, similar to the one offered in
Amazon SMP FreeRTOS.
- Various functions have been updated to use that macro
- Removed some unecessary static asserts of CONFIG_FREERTOS_NO_AFFINITY and
added casting.
- Uncrustify changes
It was noticed that when high level compiler optimizations are enabled,
the compiler optimizes some list manupulation code. This commit enables
the configLIST_VOLATILE for list elements to prevent the compiler from
optimizing out essential kernel code.
Revert "fix(freertos/idf): Add workaround for same priority preemption in xTaskIncrementTick()"
Closes IDF-8428
See merge request espressif/esp-idf!26732
This commit refactors some of the thread safety convenience macros by removing
some repeated definitions and keeping them all in "freertos_idf_additions_priv.h"
This commit mainly targets the ESP32-P4. It adds supports for coprocessors on
RISC-V based targets. The coprocessor save area, describing the used coprocessors
is stored at the end of the stack of each task (highest address) whereas each
coprocessor save area is allocated at the beginning of the task (lowest address).
The context of each coprocessor is saved lazily, by the task that want to use it.
This commit does the following:
- Update doxygen comments in FreeRTOS headers to remove unsupported doxygen
labels and internal functions
- Fixed existing doxygen warnings in FreeRTOS headers
