5 Commits

Author	SHA1	Message	Date
SalimTerryLi	874a720286	soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one ... update all struct headers to be more "standardized": - bit fields are properly wrapped with struct - bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits - bit field should be uint32_t - typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199 added helper macros to force peripheral registers being accessed in 32 bitwidth added a check script into ci	2021-08-30 13:50:58 +08:00
Cao Sen Miao	11672dc9e5	soc: update the csv headers for esp32s3	2021-06-16 18:04:18 +08:00
Marius Vikhammer	19a492bc8d	soc: add base support for ESP32-S3 ... Updates the following with changes from verification branches: * esp_rom linker files * rtc_cntl and system reg and struct headers Also updates: * GDMA driver with new register layout * esptool submodule commit	2021-06-07 10:40:14 +08:00
Marius Vikhammer	e2919eca8e	soc: add soc headers from S3 fpga bringup branch	2021-03-17 18:47:51 +08:00
Renz Bagaporo	79887fdc6c	soc: descriptive part occupy whole component	2020-10-28 07:21:29 +08:00