Commit Graph

125 Commits

Author SHA1 Message Date
morris
49e7228be9 feat(gptimer): basic driver support on esp32c5 2024-02-19 10:27:18 +08:00
Song Ruo Jing
95133c179f feat(clk): preliminary clock tree support for ESP32C5 2024-02-07 14:38:15 +08:00
laokaiyao
c0c6af99e9 fix(esp32c5): fixed the lack of crosscore ll on c5 2024-02-05 12:39:35 +08:00
Wu Zheng Hui
5454d37d49 Merge branch 'feature/support_gdma_retention' into 'master'
feature: support gdma retention in pd_top lightsleep

Closes IDF-7704 and IDFGH-11389

See merge request espressif/esp-idf!27246
2024-02-04 20:17:02 +08:00
wuzhenghui
0c2f811ca8
feat(esp_hw_support): support gdma register context sleep retention 2024-02-02 11:21:40 +08:00
Marius Vikhammer
4d28524bdb docs(esp32c5): add support for building C5 docs 2024-02-01 10:06:41 +08:00
Song Ruo Jing
cf93777077 refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
2024-01-25 19:15:33 +08:00
Wu Zheng Hui
55f04b3326 Merge branch 'feature/clean_up_retention_context_definitions' into 'master'
refactor(esp_hw_support): move sleep retention context definition to soc target folder

Closes PM-10

See merge request espressif/esp-idf!26753
2024-01-24 20:24:02 +08:00
wuzhenghui
f3f12e973c
refactor(esp_hw_support): separate different chip system peripheral regs context defs to target folder 2024-01-23 13:30:01 +08:00
wuzhenghui
9b3dc69908
refactor(esp_hw_support): move regdma structure defination to soc components 2024-01-23 11:51:44 +08:00
Mahavir Jain
9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-22 13:34:32 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
laokaiyao
d0a8f3e5c4 feat(esp32c5): support esptool on esp32c5 beta3 2024-01-09 13:11:11 +08:00
laokaiyao
3d459e423a feat(esp32c5): support esp32c5 beta3 48M xtal 2024-01-09 13:11:11 +08:00
laokaiyao
96a4ead083 feat(esp32c5): support to run hello world on esp32c5 beta3 2024-01-09 13:11:11 +08:00
laokaiyao
11e19f40b9 feat(esp32c5): support to build hello world on esp32c5 beta3 2024-01-09 13:11:11 +08:00
Song Ruo Jing
7f2b85b82b feat(clk): add basic clock support for esp32p4
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
2023-12-29 00:37:26 +08:00
laokaiyao
fcc9293f66 change(esp32c5): update soc files for esp32c5 beta3 2023-12-28 10:23:15 +08:00
laokaiyao
2b44d62e43 feat(esp32c5): support esp32c5 g0 components 2023-12-08 15:12:24 +08:00
laokaiyao
40bce13348 feat(esp32c5): update reg headers for multiple instances module (part3) 2023-12-01 19:04:55 +08:00
laokaiyao
9b31979107 feat(esp32c5): add struct name and reformat struct headers (part3) 2023-12-01 19:04:46 +08:00
Kevin (Lao Kaiyao)
15803e14e9 Merge branch 'feature/add_esp32c5_beta3_soc_header_files' into 'master'
feat(esp32c5): add esp32c5 soc header files (stage 2, part 1)

See merge request espressif/esp-idf!27492
2023-11-30 15:07:04 +08:00
laokaiyao
d87e007c66 feat(esp32c5): add esp32c5-beta3 soc header files (part1) 2023-11-29 20:53:33 +08:00
laokaiyao
87f7d2edc4 feat(esp32c5): add esp32c5-beta3 soc header files (part2) 2023-11-29 20:48:52 +08:00
laokaiyao
bb0879b3f8 feat(esp32c5): introduce target esp32c5 2023-11-28 16:14:17 +08:00