5 Commits

Author	SHA1	Message	Date
Marius Vikhammer	f8f93d936e	ulp-riscv: add support for using ADC as well as an example show-casing it.	2022-08-09 09:21:15 +08:00
Sudeep Mohanty	a0e3d488da	ulp: Added support for ULP FSM on esp32s3 and fixed bugs for esp32s2 ... This commit enables ULP FSM support for esp32s3 and updates ULP FSM code flow for other chips. It adds C Macro support for the ULP FSM instruction set on esp32s2 and esp32s3. The unit tests are also updated to test ULP FSM on ep32s2 and esp32s3.	2022-06-29 11:57:02 +08:00
intern	74d745a80b	docs: update cn trans for upl docs	2022-06-29 11:56:59 +08:00
Sudeep Mohanty	b72f987c5c	ulp: Added ULP RISC-V support for esp32s3 ... This commit adds support for ULP RISC-V for esp32s3. Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>	2022-06-22 13:33:14 +08:00
morris	61f89b97c6	bringup esp32-s3 on FPGA	2020-09-22 15:15:03 +08:00