9 Commits

Author	SHA1	Message	Date
Alexey Gerenkov	dea45a9d72	riscv: Use semihosting to set breakpoint and watchpoint when running under debugger	2022-02-24 08:55:40 +00:00
Ivan Grokhotkov	876f4d6a1c	vfs: add support for semihosting on ESP32-C3	2022-01-14 17:29:03 +01:00
Cao Sen Miao	36f6d16b8d	ESP8684: add soc, riscv, newlib support	2021-11-06 17:33:44 +08:00
Jakob Hasse	b51889dccb	system: stack watchpoint support on C3 ... Closes IDF-2307	2021-01-14 17:46:44 +08:00
morris	7a71cedf87	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
Felipe Neves	72e4655d4e	interrupt: removed descriptor table from esp32c3 interrupt hal.	2021-01-05 15:39:46 +08:00
Felipe Neves	544a3f7df5	interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available	2021-01-05 15:39:46 +08:00
Renz Bagaporo	4cc6b5571b	esp_system: support riscv panic	2020-11-13 07:49:11 +11:00
Angus Gratton	fccab8f4ef	riscv: Add new arch-level component ... Changes come from internal branch commit a6723fc	2020-11-12 09:33:18 +11:00