The Xtensa FreeRTOS port does not save the threadptr register when
doing a voluntary yield. This can result in a crash when multiple
tasks used the threadptr register and call "taskYIELD()".
This commit adds the threadptr register to the solicited stack frame.
These were called from IRAM context where the caller expect them to be inlined
and accessible when cache is disabled. This was not the case when compiled with -O0.
Closes https://github.com/espressif/esp-idf/issues/8301
xPortStartScheduler calls vPortSetupTimer -> _frxt_tick_timer_init,
which enables tick timer interrupt and sets up the first timeout.
From that point on, the interrupt can fire. If the interrupt happens
while _frxt_dispatch is running, the scheduler will enter an infinite
loop. This is because _frxt_dispatch isn't supposed to be preemptable,
and the tick interrupt will overwrite some of the registers used by
_frxt_dispatch.
Note that this situation doesn't practically occur on the real
hardware, where the execution of vPortSetupTimer and _frxt_dispatch
happens quickly enough. However it can be reproduced on an emulator
if the tick period is set to 1ms.
Add an explicit call to portDISABLE_INTERRUPTS in xPortStartScheduler
to guarantee that _frxt_dispatch doesn't run with interrupts enabled.
This is similar to the esprv_intc_int_set_threshold(1); call in
RISC-V version of port.c.
Add TRY_ENTRY_CRITICAL() API to all for timeouts when entering critical sections.
The following port API were added:
- portTRY_ENTER_CRITICAL()
- portTRY_ENTER_CRITICAL_ISR()
- portTRY_ENTER_CRITICAL_SAFE()
Deprecated legacy spinlock API in favor of spinlock.h. The following API were deprecated:
- vPortCPUInitializeMutex()
- vPortCPUAcquireMutex()
- vPortCPUAcquireMutexTimeout()
- vPortCPUReleaseMutex()
Other Changes:
- Added portMUX_INITIALIZE() to replace vPortCPUInitializeMutex()
- The assembly of the critical section functions ends up being about 50 instructions longer,
thus the spinlock test pass threshold had to be increased to account for the extra runtime.
Closes https://github.com/espressif/esp-idf/issues/5301
This commit removes the following critical nested macros as follows:
- portENTER_CRITICAL_NESTED()
- portEXIT_CRITICAL_NESTED()
They are replaced with portSET_INTERRUPT_MASK_FROM_ISR() and
portCLEAR_INTERRUPT_MASK_FROM_ISR() which are the proper FreeRTOS interfaces.
Created a portmacro_deprecated.h for each port to contain deprecated API
that were originally from portmacro.h
- port.c and portmacro.h contents are now logically grouped
- Doxygen API descriptions added
- Added refactor todo markers
- Removed portmacro_priv.h. Contents now in portmacro.h
- Formatted files
Moved FreeRTOSConfig.h from include/freertos to include/esp_additions/freertos.
Updated FreeRTOS.h file to include FreeRTOSConfig.h without the
freertos/ prefix to match with the upstream file.
Renamed architecture specific FreeRTOSConfig.h files to FreeRTOSConfig_arch.h
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt
components/os: high level interrupt(5)
components/os: hli_api: meta queue: fix out of bounds access, check for overflow
components/os: hli: don't spill registers, instead save them to a separate region
Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).
Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.
components/bt: using high level interrupt in lc
components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`
components/bt: optimize code structure
components/os: Modify the BT assert process to adapt to coredump and HLI
components/os: Disable exception mode after saving special registers
To store some registers first, avoid stuck due to live lock after disabling exception mode
components/os: using dport instead of AHB in BT to fix live lock
components/bt: Fix hli queue send error
components/bt: Fix CI fail
# Conflicts:
# components/bt/CMakeLists.txt
# components/bt/component.mk
# components/bt/controller/bt.c
# components/bt/controller/lib
# components/esp_common/src/int_wdt.c
# components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
# components/soc/esp32/include/soc/soc.h
* ##__VA_ARGS__ is replaced by __VA_OPT__(,)
and __VA_ARGS if C++20 is used.
* Affected header files are: esp_log.h,
portmacro.h and esp_check.h
* Closes https://github.com/espressif/esp-idf/pull/6692
portGET_ARGUMENT_COUNT uses a GCC extension ##__VA_ARGS__. It forces
the user to compile the code with GNU extensions enabled instead of ISO
language standard. The suggested change is to replace ##__VA_ARGS__ with
__VA_OPT__(,) __VA_ARGS__ which is supported by the current version of
GCC used in ESP-IDF for both C and C++ ISO standards.
This fix would enable ESP-IDF users to compile their code with ISO C++20
standard in future releases.
Signed-off-by: Jakob Hasse <jakob.hasse@espressif.com>
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.
Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.
Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
Fixes issue with DPORT init task, this task uses minimum stack size and may not be
enough if stack smashing detection is set to Overall mode.
Also reworks the way we calculate minimum stack to allow for adding multiple
contributing factors.
Closes https://github.com/espressif/esp-idf/issues/6403
Unless the option for "assert and keep running" is enabled.
This means that silent asserts now work for FreeRTOS, and disabling asserts
now also disables them in FreeRTOS without needing a separate config change.
Related to https://github.com/espressif/esp-idf/issues/6306
Enable shared stack watchpoint for overflow detection
Enable unit tests:
* "test printf using shared buffer stack" for C3
* "Test vTaskDelayUntil" for S2
* "UART can do poll()" for C3
