ACMD41 argument is different between SD mode and SPI mode.
In SPI mode, the only non-zero bit may be the HCS bit. Unlike the SD
mode, the bits reflecting the host's OCR should be zero.
Previously, we used to set these bits the same way as for the SD mode.
This has caused certain cards to fail initializing, apparently their
controllers have checked the ACMD41 argument more strictly and refused
to finish initialization, resulting in an error such as
sdmmc_common: sdmmc_init_ocr: send_op_cond (1) returned 0x107
(Note that this error may have other causes than the one fixed in
this commit. For example, if the card doesn't have a sufficient and
stable power supply, it may also fail to complete the internal
initialization process, and will never clear the busy flag in R1
response.)
Closes https://github.com/espressif/esp-idf/issues/6686
Closes https://github.com/espressif/esp-idf/issues/10542
Previous version of the code used a fixed constant (500 ms) for the
erase timeout and added 1 ms for each sector erased.
This commit improves timeouts calculation:
- For SD cards, check if erase timeout information is present in the
SSR register. If yes, use it for erase timeout calculation.
Otherwise assume 250ms per erase block, same as Linux does.
- For eMMC assume 250ms per erase block (but no less than 1 second).
This has to be improved later to use the erase timeout info in the
extended CSD register.
options.
Erase command (38) for SD cards allows option for erase/dicard/fule
operation at block level and for MMC cards supports option for
discard/trim at block level. When Sanitize is executed only the
portion of data that was unmapped by a Discard command shall be
removed by the Sanitize command.
Unit test cases added to verify ERASE feature in SD/SDSPI mode.
TRIM/DISCARD/SANITIZE tests for eMMC devices.
Closes https://github.com/espressif/esp-idf/pull/7635
Closes https://github.com/espressif/esp-idf/issues/7623
Works for 3.3V eMMC in 4 line mode.
Not implemented:
- DDR mode for SD cards (UHS-I) also need voltage to be switched to 1.8V.
- 8-line DDR mode for eMMC to be implemented later.
