alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity
22,374 Commits 20 Branches 148 Tags 384 MiB
bff43a1b6f
Commit Graph

4 Commits

Author SHA1 Message Date
Sudeep Mohanty
96b152a01f ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2 
This commit fixes an issue where in the ULP RISC-V I2C example causes
a spurious wakeup of the main CPU because of a Trap signal when the ULP
core does not meet the wakeup threshold values. This was due to the fact
that the RTC_CNTL_COCPU_DONE signal was being set before the
RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V
core to not reset properly on each cycle.

Closes https://github.com/espressif/esp-idf/issues/10301
 2023-01-02 14:24:16 +01:00
Marius Vikhammer
386739595f RISCV-ULP: Add DS18B20 1wire RISCV-ULP example 2021-06-25 11:26:39 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit) 
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
 2020-11-11 07:36:35 +00:00
Felipe Neves
b6dba84323 ulp: added support to building code for riscv ULP coprocessor 2020-07-15 15:28:49 -03:00