Commit Graph

26 Commits

Author SHA1 Message Date
XiaXiaotian
9d8425bd72 put RODATA of libphy.a into DRAM
There are some RODATAs of libphy.a that are called in ISR. So need
    to put them into DRAM to avoid access them when R/W SPI flash. Due
    to the RODATAs which are called in ISR haven't been picked out to
    put into DRAM, put all of the RODATA of libphy.a into DRAM. This
    will be optimized in the future.
2017-04-24 11:22:49 +08:00
XiaXiaotian
b238bc691d Do not put the whole object files into IRAM. Add attributes to the functions called in ISR instead. 2017-04-21 15:38:01 +08:00
Alexey Gerenkov
55f1a63faf esp32: Adds functionality for application tracing over JTAG
- Implements application tracing module which allows to send arbitrary
   data to host over JTAG. This feature is useful for analyzing
   program modules behavior, dumping run-time application data etc.
 - Implements printf-like logging functions on top of apptrace module.
   This feature is a kind of semihosted printf functionality with lower
   overhead and impact on system behaviour as compared to standard printf.
2017-04-17 23:26:29 +03:00
Ivan Grokhotkov
9edab21385 Merge branch 'feature/rtc_clk_impl' into 'master'
Introduce soc component, add source of rtc_clk and rtc_pm libraries

This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.

Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.

Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.

See merge request !633
2017-04-12 10:38:23 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Jiang Jiang Jian
8ee6f8227e Merge branch 'bugfix/reset_mac_cause_bt_cannot_rx_data' into 'master'
Reset WIFI mac when wifi start and update wifi lib

1. reset wifi mac when wifi start

2. roll back rx hung workaround for beacon timeout

3. fix amsdu ap interface wrong issue

4. fix amsdu header parse error

5. fix amsdu flag wrong issue

6. PHY: V350, fix BT rssi bug

7. RTC: V225, fix bt will be not work when wifi is reset

See merge request !606
2017-03-24 17:02:26 +08:00
Ivan Grokhotkov
710c853adc Merge branch 'bugfix/spi_flash_lock_period' into 'master'
SPI flash operations lock for shorter periods

Based on bug report here:
https://esp32.com/viewtopic.php?f=13&t=1489&p=6816#p6773

Long SPI flash erase (and possibly write/read) cycles block all tasks on both CPUs for an extended period, and can lead to WiFi dissassociation (and general priority inversion.)

This MR inserts preemption breaks into large operations (all erases, writes every 8KB, reads every 16KB).

Overhead of a single spi_flash_guart_start()/spi_flash_guard_end() cycle measured at approx 67us (assuming no preemption.)

See merge request !600
2017-03-24 15:55:42 +08:00
Angus Gratton
0e31eb458e esp32: Move heap_alloc_caps to IRAM
Rest of malloc() path was already in IRAM
2017-03-24 10:41:45 +08:00
XiaXiaotian
6181c39f05 Reset WIFI mac when wifi start and update wifi lib
1. reset wifi mac when wifi start

2. roll back rx hung workaround for beacon timeout

3. fix amsdu ap interface wrong issue

4. fix amsdu header parse error

5. fix amsdu flag wrong issue

6. PHY: V350, fix BT rssi bug

7. RTC: V225, fix bt will be not work when wifi is reset
2017-03-23 14:28:27 +08:00
Angus Gratton
6afea0e81c linker scripts: Add explicit symbols for _iram_start and _flash_cache_start
This is to avoid confusion when idf_monitor prints the first symbol in each section, ie "WindowOverflow4" or similar,
when bootloader prints the section mapping address.

Closes #447 https://github.com/espressif/esp-idf/issues/447
2017-03-21 16:45:13 +08:00
XiaXiaotian
a51f378ecc bugfix: it causes exception that wifi interrupt happens when read/write flash, if pp_post() is on icache. 2017-02-21 14:25:34 +08:00
XiaXiaotian
eb14284c92 disable PHY and RF when stop WiFi and disable BT
1. Add disable PHY and RF when WiFi and BT are both disabled(including call sniffer disable API).

2. Do not init PHY and RF when cpu start. Init PHY and RF when call Wifi or BT start APIs(including sniffer enable API).

3. Add a temporary lib: librtc_clk.a and will delete it when CPU frequency switching function is done.

4. Add an function to get OS tick rate.

5. Do not put the whole pp.a in iram0, only put lmac.o, ieee80211_misc.o, ets_time.o and wdev.o in iram0.
2017-02-17 10:24:54 +08:00
Alexey Gerenkov
04acc88023 esp32: Fixes watchdog problem when printing core dump to uart
Also fixes generation of core dumps when flash cache is disabled
2017-02-01 18:39:28 +03:00
Tian Hao
2bb67985dc component/bt : move some codes of controller to iram
1. mv codes which called by sir into iram
2. mv libcoexist.a into iram
2017-01-18 16:38:06 +08:00
Ivan Grokhotkov
9aa0e29079 deep sleep: keep RTC_SLOW_MEM powered on if data is placed into RTC slow memory 2017-01-12 14:15:30 +08:00
Liu Zhi Fu
a575b9e893 esp32: modify ld file to fix a crash issue 2017-01-07 16:12:07 +08:00
Ivan Grokhotkov
61c6ce86d2 esp32: put .data before .bss
This change reduces chances that a large .bss segment will push .data all the way into
0x3ffe1320 — 0x3ffe5320 range where the bootloader stack is, creating a problem when
bootloader will be loading application into memory.
With this change, .data would need to be at least 200k big to cause problems.
2017-01-06 13:46:06 +08:00
Angus Gratton
5e96070c27 linker script: Remove KEEP from RAM-resident sections
Reduce RAM usage when not all data/bss sections in source files were used.
2017-01-03 11:02:12 +11:00
Ivan Grokhotkov
f18c1f13b1 Merge branch 'feature/deepsleep_stub_linker' into 'master'
Deep sleep: Any source named rtc_wake_stub* is linked as RTC wake stub code

Also move esp_deepsleep.h documentation out to docs/deep-sleep-stub.rst

See merge request !142
2016-11-01 22:27:13 +08:00
Jeroen Domburg
309bd12855 Re-add panic.o to IRAM/DRAM. 2016-10-28 14:32:11 +08:00
Ivan Grokhotkov
999e6d4e8f freertos: move panic handler data to DRAM
Fixes https://ezredmine.espressif.com/issues/7817
2016-10-27 17:57:29 +08:00
Angus Gratton
da70611196 Deep sleep: Any source named rtc_wake_stub* is linked as RTC wake stub code
Also move esp_deepsleep.h documentation out to docs/deep-sleep-stub.rst
2016-10-19 15:58:37 +11:00
Angus Gratton
7c494055e3 esp32: Bootloader wake deep sleep stub
App can contain a stub program resident in RTC fast memory. Bootloader
will load the stub on initial boot. If the device wakes from deep sleep,
the stub is run immediately (before any other data is loaded, etc.)

To implement a custom wake stub, implement a function in your program:

```
void RTC_IRAM_ATTR esp_wake_deep_sleep(void)
{
  esp_default_wake_deep_sleep();
  // other wake logic
}
```

... and it will replace the default implementation.
2016-09-28 11:14:58 +08:00
Ivan Grokhotkov
62aaec630c components/esp32: remove "_user" part from entry points, weaken start_cpu0/1
With this change applications can override very early part of startup procedure by implementing "start_cpu0" and "start_cpu1" functions.
2016-09-26 12:29:00 +08:00
Wu Jian Gang
c3102e8fb2 ld: seperate/rename eagle.xxx.ld to esp32.xxx.ld 2016-08-25 11:07:53 +08:00