Commit Graph

7 Commits

Author SHA1 Message Date
Cao Sen Miao
e226a65a1f spi_flash: add support for 32Mbit address GD flash, for GD25Q256 2021-10-12 10:53:07 +08:00
Cao Sen Miao
4906779d50 spi_flash: make suspend off by default and add more information for using suspend 2021-03-29 12:02:43 +08:00
Cao Sen Miao
f3e79ca166 spi_flash(c3): add boya chip support for suspend feature 2021-01-25 11:14:06 +08:00
Angus Gratton
d4c9a45675 spi_flash: Add ESP32-C3 support
Based on internal commit 3ef01301fff
2020-12-17 15:34:13 +11:00
Michael (XIAO Xufeng)
3bacf35310 esp_flash: support high capacity flash chips (32-bit address) 2020-10-29 18:20:11 +08:00
Michael (XIAO Xufeng)
a9c8895bb2 esp_flash: refactor to be compatible with the latest ROM
Including:
1. Change the write bytes/read bytes parameter in the host driver into slicers to meet the requirements of complicated cases.
2. Refactor the esp_flash_api code a bit so that we can use the code in the ROM laster
3. Provide get_temp_buffer and release_temp_buffer in the os_functions when the buffer passed by application cannot be used directly.
4. Make timeout of operations configurable in the chip_driver.
5. Make dummy number configurable.
2020-07-12 02:09:45 +08:00
Michael (XIAO Xufeng)
3b429766bc esp_flash: support MXIC flash chips
The default chip driver (chip_generic) use command 01H + 2 bytes to
clear the QE bit. However this will accidently change the configuration
register value of the MXIC chip.

MXIC chip driver is added to fix that.
2020-04-01 20:54:23 +08:00