Commit Graph

25 Commits

Author SHA1 Message Date
Martin Vychodil
ec6745a137 System/Security: wrong check of the Memprot feature in esp_restart()/panic_restart()
esp_restart()/panic_restart() never resets the Digital system (so far required only by the Memprot feature) as there's a typo in the corresponding #define:
it checks CONFIG_ESP_SYSTEM_CONFIG_MEMPROT_FEATURE instead of CONFIG_ESP_SYSTEM_MEMPROT_FEATURE.
Issue fixed.

IDF-4094
2021-10-05 11:58:31 +02:00
Angus Gratton
1fc288556c esp_system: Reconfigure the WDTs at the start of the panic handler
This is mostly important on ESP32 ECO3 with the
ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core
before we disable the TG1 WDT then the first CPU can get stuck
in WDT ISR handle_livelock_int routine waiting for the other CPU.
2021-07-06 09:59:39 +08:00
Martin Vychodil
69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00
Omar Chebib
c218f669ba panic on RISC-V: Take into account Merge Request comments 2020-12-31 15:46:17 +08:00
Ivan Grokhotkov
5962b1dc56 panic: print register dump on abort for RISC-V
Register values are necessary to perform host-side backtracing on
RISC-V. Print them in case of an abort as well.
2020-12-31 15:46:17 +08:00
Omar Chebib
b6a450f824 panic: Add support for SoC-level panic
SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
2020-12-31 15:46:17 +08:00
Renz Bagaporo
4cc6b5571b esp_system: support riscv panic 2020-11-13 07:49:11 +11:00
Angus Gratton
420aef1ffe Updates for riscv support
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
Martin Vychodil
497b730e8f * memprot support for RTC_SLOW
* API upgrade
JIRA IDF-1636
2020-10-08 11:19:23 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
Ivan Grokhotkov
5ff9cd495e panic: skip over the first invalid PC in case of InstrFetchProhibited
InstrFetchProhibited usually occurs because of a jump to an invalid
pointer. In this case, PC in the exception frame is the address of
the jump destination. 'esp_ptr_executable' check in print_backtrace
function recognizes the first frame as invalid, and the backtrace is
interrupted. This prevents the user from finding the location where
the invalid pointer is dereferenced.

Bypass the 'esp_ptr_executable' check if the exception cause is
InstrFetchProhibited. Update the test case to no longer ignore this
issue.
2020-08-05 12:00:50 +02:00
Ivan Grokhotkov
8ac56e904b Merge branch 'bugfix/coredump_esp_panic_reason' into 'master'
Coredump ESP panic reason

See merge request espressif/esp-idf!9072
2020-07-28 23:49:10 +08:00
Alexey Gerenkov
21091c6b0e coredump: Fixes ESP-specific panic reasons handling 2020-07-27 21:38:33 +03:00
morris
2917651478 esp_rom: extract common ets apis into esp_rom_sys.h 2020-07-27 15:27:01 +08:00
morris
345606e7f3 esp_rom: extract common uart apis into esp_rom_uart.h 2020-07-17 16:00:59 +08:00
Renz Christian Bagaporo
08ad0f8194 esp_system: remove usage of CONFIG_FREERTOS_UNICORE from panic handler 2020-07-06 15:33:56 +08:00
Sachin Parekh
46d914ff45 gdb: Modify PC in case of invalid PC
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-05-08 18:34:52 +05:30
Ivan Grokhotkov
c5f664d4ac esp_system: remove duplicated esp_digital_reset function
esp_digital_reset was defined both in system_api.c and panic_handler.c
2020-05-04 10:13:14 +00:00
Ivan Grokhotkov
8bdfb265a4 panic handler: fix cache error handling 2020-05-04 10:13:14 +00:00
Martin Vychodil
7491ea677a esp32s2: IRAM/DRAM memory protection
* new mem_prot API
* mem_prot on & locked by default (see Kconfig)
* feature activated in start_cpu0_default()

JIRA IDF-1355
2020-04-21 15:10:58 +02:00
Darian Leung
91841a53ff WDT: Add LL and HAL for watchdog timers
This commit updates the watchdog timers (MWDT and RWDT)
in the following ways:

- Add seprate LL for MWDT and RWDT.
- Add a combined WDT HAL for all Watchdog Timers
- Update int_wdt.c and task_wdt.c to use WDT HAL
- Remove most dependencies on LL or direct register access
  in other components. They will now use the WDT HAL
- Update use of watchdogs (including RTC WDT) in bootloader and
  startup code to use the HAL layer.
2020-03-26 02:14:02 +08:00
Renz Bagaporo
ee519634a5 esp_system: retain backtrace no space 2020-03-10 19:56:24 +08:00
Renz Bagaporo
890510aecd esp32, esp32s2: move reset reason source to esp_system 2020-03-10 19:56:24 +08:00
Renz Christian Bagaporo
af9b1131a3 esp_system: share abort panic with port layer 2020-03-10 19:56:24 +08:00
Renz Christian Bagaporo
2b100789b7 esp32, esp32s2: move panic handling code to new component 2020-03-10 19:56:24 +08:00