Commit Graph

14 Commits

Author SHA1 Message Date
KonstantinKondrashov
1687c53700 freertos: Fix save_context. Add RSYNC after WSR
RSYNC waits for all previously fetched WSR.* instructions to be performed before inter-
preting the register fields of the next instruction.
2019-12-21 14:10:38 +00:00
Felipe Neves
64a50f0423 components/freertos: fixed isr test failling when run multiple times 2019-12-04 10:40:27 -03:00
Felipe Neves
bcdc35be59 components/freertos: refactor of isr_latency tests to perform full measurement 2019-12-04 10:39:22 -03:00
Felipe Neves
8b6b97ec57 freertos/xtensa_context: fixed small typo 2019-12-04 10:39:22 -03:00
Felipe Neves
c14fc39b0a components/freertos: fixed typos and licence placement on external code 2019-12-04 10:39:22 -03:00
Felipe Neves
64f918bd70 freertos/xtensa_context: added conditional compiling option around isr cycle measurement
It is possible to enable and disable the isr time measurement on context save and
it related test via menuconfig by the new option: FREERTOS_ISR_STATS
2019-12-04 10:39:22 -03:00
Felipe Neves
346b12e29a freertos/test: added spill register timer measurement test 2019-12-04 10:39:22 -03:00
Felipe Neves
5ce7a33c87 freertos/xtensa_context.S: fix some dread tabs 2019-12-04 10:39:22 -03:00
Felipe Neves
cd11787153 freertos/xt_asm_utils: added documentation of current windows spill solution 2019-12-04 10:39:22 -03:00
Felipe Neves
768d115e85 freertos/Kconfig: removed isr optimization option from menuconfig 2019-12-04 10:39:22 -03:00
Felipe Neves
eb740ca8e4 freertos/xtensa_context: modification of interrupt handler is workin, needs stabilization 2019-12-04 10:39:22 -03:00
Felipe Neves
d185625162 freertos/xtensa_context: added infrastructure to receive the spill register optimized code 2019-12-04 10:39:22 -03:00
jack
fc130fba86 fix bug that files missing commit in MR 773 2017-05-31 19:37:39 +08:00
Ivan Grokhotkov
bd6ea4393c Initial public version 2016-08-17 23:08:22 +08:00