KonstantinKondrashov
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1687c53700
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freertos: Fix save_context. Add RSYNC after WSR
RSYNC waits for all previously fetched WSR.* instructions to be performed before inter-
preting the register fields of the next instruction.
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2019-12-21 14:10:38 +00:00 |
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Felipe Neves
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64a50f0423
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components/freertos: fixed isr test failling when run multiple times
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2019-12-04 10:40:27 -03:00 |
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Felipe Neves
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bcdc35be59
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components/freertos: refactor of isr_latency tests to perform full measurement
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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8b6b97ec57
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freertos/xtensa_context: fixed small typo
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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c14fc39b0a
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components/freertos: fixed typos and licence placement on external code
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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64f918bd70
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freertos/xtensa_context: added conditional compiling option around isr cycle measurement
It is possible to enable and disable the isr time measurement on context save and
it related test via menuconfig by the new option: FREERTOS_ISR_STATS
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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346b12e29a
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freertos/test: added spill register timer measurement test
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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5ce7a33c87
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freertos/xtensa_context.S: fix some dread tabs
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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cd11787153
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freertos/xt_asm_utils: added documentation of current windows spill solution
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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768d115e85
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freertos/Kconfig: removed isr optimization option from menuconfig
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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eb740ca8e4
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freertos/xtensa_context: modification of interrupt handler is workin, needs stabilization
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2019-12-04 10:39:22 -03:00 |
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Felipe Neves
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d185625162
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freertos/xtensa_context: added infrastructure to receive the spill register optimized code
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2019-12-04 10:39:22 -03:00 |
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jack
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fc130fba86
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fix bug that files missing commit in MR 773
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2017-05-31 19:37:39 +08:00 |
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Ivan Grokhotkov
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bd6ea4393c
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Initial public version
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2016-08-17 23:08:22 +08:00 |
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