Commit Graph

2146 Commits

Author SHA1 Message Date
Nachiket Kukade
413bcd8fcd feat(esp_wifi): Refactor and improve FTM code
Enable FTM Responder mode for ESP32C6. Update wifi libs with below -

1. Break FTM State Machine code into separate functions
2. Use dynamic allocation for FTM session to save memory
3. Add API to get FTM report instead of event based mechanism
4. Add FTM Request retry and comeback support
2024-03-26 18:00:10 +05:30
Jiang Jiang Jian
2d818bbfe5 Merge branch 'docs/rf_coexistence_api_guides_support_esp32c2_v5.2' into 'release/v5.2'
Docs: RF coexistence api guides support esp32c2 (v5.2)

See merge request espressif/esp-idf!29213
2024-03-11 10:40:40 +08:00
Jiang Jiang Jian
a15fd9846b Merge branch 'fix/bbpll_usb_link_error_backport5.2' into 'release/v5.2'
fix(esp_phy): Allow WiFi/USB interference workaround option only on supported targets (backport v5.2)

See merge request espressif/esp-idf!29481
2024-03-11 10:22:26 +08:00
Marius Vikhammer
9e5c30baff Merge branch 'bugfix/reset_reasons_v5.2' into 'release/v5.2'
Update reset reasons for C6, H2, P4 and C5 (v5.2)

See merge request espressif/esp-idf!29180
2024-03-08 09:42:36 +08:00
Tomas Rezucha
bbb549c830 fix(esp_phy): Allow WiFi/USB interference workaround option only on supported targets
"Enable USB when phy init" Kconfig option would call esp_phy function
`phy_bbpll_en_usb()` that is not implemented for all targets.
Selecting this option for unsupported target results in linking error.

The necessity of this workaround is now defined soc_caps.h rather than
in the Kconfig.

Closes https://github.com/espressif/esp-idf/issues/12185
2024-03-07 12:47:39 +01:00
linruihao
3d5852131b fix(esp_coex): add support_coexistence soc_caps for esp32c2 and esp32h2 2024-02-23 16:15:45 +08:00
Jiang Jiang Jian
8e1cd38970 Merge branch 'c6_auto_dbias_master_hsq_v5.2' into 'release/v5.2'
ESP32C6: Active & sleep dbg and dbias get from efuse to fix the voltage (v5.2)

See merge request espressif/esp-idf!28729
2024-02-22 20:04:08 +08:00
hongshuqing
b3a73d5b63 feat(pmu): set fix voltage to different mode for esp32c6 2024-02-22 14:49:01 +08:00
Marius Vikhammer
e930ff0b1f fix(system): update reset reasons for C6 and H2 2024-02-22 12:37:49 +08:00
Cao Sen Miao
4df78f9cff fix(temperature_sensor): Cannot switch the range smmothly on esp32h2 2024-02-21 18:51:29 +08:00
Jiang Jiang Jian
3c7c5829b7 Merge branch 'h2_auto_dbias_master_hsq_v5.2' into 'release/v5.2'
ESP32H2: Active & sleep dbias get from efuse to fix the voltage (v5.2)

See merge request espressif/esp-idf!28714
2024-02-21 10:49:16 +08:00
Darian Leung
471fe41828
refactor(soc): Remove soc/usb_types.h
This header has been removed for the following reasons:

- Header is misplaced. 'xxx_types.h' headers should be placed in the 'hal'
component.
- The 'usb_xxx_endpoint_t' should be placed in the 'xxx_struct.h' header.
2024-02-19 15:45:04 +08:00
Darian Leung
b07a43e630
refactor(soc): Rename usb_otg_periph to usb_dwc_periph
- Renamed usb_otg_periph.h/c to usb_dwc_periph.h/c to match naming convention
of other DWC OTG related files
- Added compatibility header for usb_otg_periph.h
2024-02-19 15:45:04 +08:00
Darian Leung
50b3a35c52
refactor(soc): Deprecate usb pin mappings
usb_pins.h and usb_periph.h/c lists mappings of USB DWC signals to GPIOs used
to connect to external FSLS PHYs. However, those signals can be routed to any
GPIOs via the GPIO matrix. Thus, these mapping are meaningless and have been
deprecated.
2024-02-19 15:45:03 +08:00
Darian Leung
f0219b73f9
refactor(hal/usb): Rename usb_fsls_phy API to match header/source names
Note: Also fixed some formatting issues in usb_wrap_struct.h
2024-02-19 15:45:02 +08:00
Darian Leung
d08b90c5cc
refactor(soc/host): Update USB OTG struct fields
This commit updates the "*_struct.h" files for the USB OTG peripheral:

- Added/removed some missing/non-existing register fields
- Added "reserved" place holders for registers that are missing due to IP
configuration.
- Added "usb_dwc_cfg.h" listing the USB OTG IP configuration for each target.
- Updated LL/HAL according to register field updates. Also tidied up the include
directives in those headers.
2024-02-19 15:45:00 +08:00
morris
81dc597d1f Merge branch 'bugfix/fix_incorrect_regbase_name_of_i2s_v5.2' into 'release/v5.2'
fix(i2s): fixed incorrect reg base name on C3 (v5.2)

See merge request espressif/esp-idf!28629
2024-02-18 11:29:42 +08:00
Mahavir Jain
e173895618 fix(soc): change debug addr range to CPU subsystem range
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-29 13:57:04 +08:00
laokaiyao
66d7410051 fix(i2s): fixed incorrect reg base name on C3
Closes https://github.com/espressif/esp-idf/issues/12643
2024-01-26 18:44:38 +08:00
KonstantinKondrashov
64b1bd6cb2 feat(efuse): Adds new efuses for esp32c6 2024-01-26 11:36:57 +08:00
KonstantinKondrashov
bc6072c754 feat(efuse): Adds new efuse for esp32h2 2024-01-26 11:36:56 +08:00
Roshan Bangar
962b105be5 fix(nimble): Added periodic_adv_enh soc_caps for c2, h2 2023-12-26 10:09:12 +05:30
Jiang Jiang Jian
99d10ca3d2 Merge branch 'change/change_regdma_power_issue_macro_v5.2' into 'release/v5.2'
change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG (backport v5.2)

See merge request espressif/esp-idf!27992
2023-12-25 20:38:48 +08:00
Jiang Jiang Jian
3139ae0f0e Merge branch 'backport/openthread_related_feature_v52' into 'release/v5.2'
Backport some openthread related features (backport v5.2)

See merge request espressif/esp-idf!28053
2023-12-25 20:37:03 +08:00
morris
b893744fd1 fix(gdma): reserve the SOC_GDMA_PAIRS_PER_GROUP
Closes https://github.com/espressif/esp-idf/issues/12798
2023-12-21 15:17:54 +08:00
Xu Si Yu
6b8740ae8d feat(ieee802154): add tx/rx report for IEEE802.15.4 debug 2023-12-21 15:01:44 +08:00
Lou Tianhao
7b5799830c change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG 2023-12-19 11:52:25 +08:00
Aditya Patwardhan
ff8a6a5bf9 Merge branch 'fix/esp32s3_soc_drom_high_addr_v5.2' into 'release/v5.2'
fix(soc): esp32s3/Fix the DROM_HIGH_ADDR (v5.2)

See merge request espressif/esp-idf!27821
2023-12-15 15:48:17 +08:00
Jiang Jiang Jian
6a34106488 Merge branch 'contrib/github_pr_12559_v5.2' into 'release/v5.2'
fix(spi): correct macro REG_SPI_BASE(i) for all targets (GitHub PR) (v5.2)

See merge request espressif/esp-idf!27708
2023-12-11 16:01:48 +08:00
Aditya Patwardhan
ebcb490aa9
fix(soc): esp32s3/Fix the DROM_DROM_HIGH limit
Previously the DROM_HIGH_ADDR for esp32s3 was 0x3D000000, which
    convers only 16 MB of address range. But esp32s3 supports 32 MB
    external memory. So this address should be 0x3E000000
2023-12-11 12:17:12 +05:30
Darian Leung
a7e2ea76d8 change(soc): Add SOC_HP_CPU_HAS_MULTIPLE_CORES
This commit adds a the SOC_HP_CPU_HAS_MULTIPLE_CORES convenience macro to
soc_caps.h. This is a convenience boolean cap to represent whether or not the
target has multiple cores, and is intended to be used when writing docs for
multiple targets.
2023-12-07 17:53:18 +08:00
morris
61bd19b446 Merge branch 'bugfix/fix_adc_cali_error_after_light_sleep_wake_on_h2_v5.2' into 'release/v5.2'
adc: fix calibration error when waking up from light sleep on H2 and enable test (v5.2)

See merge request espressif/esp-idf!27602
2023-12-07 14:29:55 +08:00
Mahavir Jain
37bf8dff6b Merge branch 'fix/esp32p4-memory-layout_v5.2' into 'release/v5.2'
fix(heap): Update the heap memory layout on esp32p4 target (backport v5.2)

See merge request espressif/esp-idf!27097
2023-12-07 11:52:14 +08:00
Jiang Jiang Jian
968b15d380 Merge branch 'fix/rng_register_prefix_discrepency_newer_targets_v5.2' into 'release/v5.2'
Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2 (v5.2)

See merge request espressif/esp-idf!27683
2023-12-07 10:46:15 +08:00
wanlei
572a66b62e fix(spi): correct some signals and dummy bits docs 2023-12-06 16:05:36 +08:00
TD-er
a4bfa19ebd fix(spi): Correct REG_SPI_BASE(i) macro for all targets
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
2023-12-06 14:44:26 +08:00
Guillaume Souchere
66759438a9 fix(heap): Update the heap memory layout on esp32p4 target
- fix the value of SOC_ROM_STACK_START in soc.h
- Update the memory usage of ROM bootloader appendix in bootloader.ld
- Update the soc_memory_regions table to minimize the number of regions
  created after the startup stack is added back as a heap.
2023-12-06 04:48:00 +00:00
Darian Leung
e9c617fa19 refactor(soc): SOC_USB_PERIPH_NUM option
This commit refactors SOC_USB_PERIPH_NUM as follows:

- Renamed to SOC_USB_OTG_PERIPH_NUM to avoid confusion with USB Serial JTAG
- Updated to unsigned integer "1U"
- Updated some build rules to depend on SOC_USB_OTG_SUPPORTED instead
2023-12-05 16:44:46 +01:00
harshal.patil
a168fde297
fix(soc/esp32h2): Fix llperi_rng_data field discrepancy 2023-12-05 21:08:33 +05:30
harshal.patil
8558aa4414
fix(soc/esp32c6): Fix llperi_rng_data field discrepancy 2023-12-05 21:08:32 +05:30
gaoxu
44f266693a fix(adc): restore cali registers after light sleep wake up on H2 and enable test 2023-12-04 12:03:49 +08:00
Song Ruo Jing
55ed548cc6 fix(console): enable to select UART1 port for console output
This feature was only enabled for esp32, esp32s2, esp32s3 previously.
Now, enabling this feature for all targets.
2023-11-30 11:26:09 +08:00
Mahavir Jain
d3b4acf7a0 fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose
In ESP32-H2, the ECDSA peripheral by default uses the TRNG (hardware)
generated k value but it can be overridden to software supplied k.
This can happen through by overriding the `ECDSA_SOFTWARE_SET_K` bit
in the configuration register. Even though the HAL API is not exposed
for this but still it could be achieved by direct register
programming. And for this scenario, if sufficiently random k is not
supplied by the software then it could posses a security risk.

In this change, we are unconditionally programming the efuse
`ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K` bit during startup security
checks itself. Additionally, same is ensured in the `esp_efuse_write_key`
API as well. This always enforces the hardware k mode in the ECDSA
peripheral and ensures strongest possible security.
2023-11-17 07:13:53 +00:00
wuzhenghui
600986cf49
fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting 2023-11-16 20:23:57 +08:00
wuzhenghui
4379d26f65
change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 20:23:57 +08:00
muhaidong
9583c45947 fix(wifi): fix deinit init wifi scan fail issue 2023-11-14 19:29:03 +08:00
gaoxu
7f3221aa09 feat(adc_cali): Add ADC calibration support for ESP32H2 2023-11-06 10:57:36 +08:00
Jin Cheng
b9ed6f722b feat(bt/bluedroid): Added mode to use BlueDroid host only without Bluetooth Controller 2023-11-02 11:10:24 +08:00
morris
80997d5860 fix(i2c): read write FIFO memory by volatile 2023-10-30 10:34:43 +08:00
Konstantin Kondrashov
a304cc230e Merge branch 'feature/esp32h2_adds_adc_calib_efuses' into 'master'
feat(efuse): Adds efuse ADC calibration data for ESP32H2

See merge request espressif/esp-idf!26305
2023-10-25 15:58:24 +08:00