Increase LP_UART_EMPTY_THRESH_DEFAULT value to 4. The original value
could cause the FIFO become empty before filling next data into the FIFO
when the buadrate is high. TX_DONE interrupt would raise before actual
transmission complete in such case.
Enable FTM Responder mode for ESP32C6. Update wifi libs with below -
1. Break FTM State Machine code into separate functions
2. Use dynamic allocation for FTM session to save memory
3. Add API to get FTM report instead of event based mechanism
4. Add FTM Request retry and comeback support
"Enable USB when phy init" Kconfig option would call esp_phy function
`phy_bbpll_en_usb()` that is not implemented for all targets.
Selecting this option for unsupported target results in linking error.
The necessity of this workaround is now defined soc_caps.h rather than
in the Kconfig.
Closes https://github.com/espressif/esp-idf/issues/12185
This header has been removed for the following reasons:
- Header is misplaced. 'xxx_types.h' headers should be placed in the 'hal'
component.
- The 'usb_xxx_endpoint_t' should be placed in the 'xxx_struct.h' header.
- Renamed usb_otg_periph.h/c to usb_dwc_periph.h/c to match naming convention
of other DWC OTG related files
- Added compatibility header for usb_otg_periph.h
usb_pins.h and usb_periph.h/c lists mappings of USB DWC signals to GPIOs used
to connect to external FSLS PHYs. However, those signals can be routed to any
GPIOs via the GPIO matrix. Thus, these mapping are meaningless and have been
deprecated.
This commit updates the "*_struct.h" files for the USB OTG peripheral:
- Added/removed some missing/non-existing register fields
- Added "reserved" place holders for registers that are missing due to IP
configuration.
- Added "usb_dwc_cfg.h" listing the USB OTG IP configuration for each target.
- Updated LL/HAL according to register field updates. Also tidied up the include
directives in those headers.
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).
For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.
For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
Previously the DROM_HIGH_ADDR for esp32s3 was 0x3D000000, which
convers only 16 MB of address range. But esp32s3 supports 32 MB
external memory. So this address should be 0x3E000000
This commit adds a the SOC_HP_CPU_HAS_MULTIPLE_CORES convenience macro to
soc_caps.h. This is a convenience boolean cap to represent whether or not the
target has multiple cores, and is intended to be used when writing docs for
multiple targets.
