alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity
18,958 Commits 20 Branches 148 Tags 384 MiB
af61c51385
Commit Graph

122 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
af61c51385 Merge branch 'test/rtc_8m_d256_v4.3' into 'release/v4.3' 
rtc: fixed 8MD256 can't be used as RTC slow src on ESP32 (v4.3)

See merge request espressif/esp-idf!18106
 2022-11-12 00:45:11 +08:00
Michael (XIAO Xufeng)
7931c033ed pm: fixed RTC8M domain power issues 
introduced in e44ead5356

1. The int8M power domain config by default is PD. While LEDC is using
RTC8M as clock source, this power domain will be kept on.

But when 8MD256 is used as RTC clock source, the power domain should
also be kept on.

On ESP32, there was protection for it, but broken by commit
e44ead5356. Currently the power domain
will be forced on when LEDC is using RTC8M as clock source &&
!int8m_pd_en (user enable ESP_PDP_DOMAIN_RTC8M in lightsleep). Otherwise
the power domain will be powered off, regardless of RTC clock source.

In other words, int8M domain will be forced off (even when 8MD256
used as RTC clock source) if LEDC not using RTC8M as clock source, user
doesn't enable ESP_PDP_DOMAIN_RTC8M, or in deep sleep.

On later chips, there's no such protection, so 8MD256 could't be used as
RTC clock source in sleep modes.

This commit adds protection of 8MD256 clock to other chips. Fixes the
incorrect protection logic overriding on ESP32. Now the power domain
will be determiend by the logic below (order by priority):

    1. When RTC clock source uses 8MD256, power up
    2. When LEDC uses RTC8M clock source, power up
    3. In deepsleep, power down
    4. Otherwise determined by user config of ESP_PDP_DOMAIN_RTC8M,
       power down by default. (This is preferred to have highest
       priority, but it's kept as is because of current code structure.)

2. Before, after the macro `RTC_SLEEP_CONFIG_DEFAULT` decides dbias, the
protection above may force the int8m PU. This may cause the inconsistent
of dbias and the int8m PU status.

This commit lifts the logic of pd int8m/xtal fpu logic to upper layer
(sleep_modes.c).

Related: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089

temp
 2022-11-05 20:02:53 +08:00
Michael (XIAO Xufeng)
b56b459960 rtc: fixed 8MD256 can't be used as RTC slow src on ESP32 
Sync configuration from other chips

Closes: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089
 2022-11-04 12:37:45 +08:00
morris
9a9f503c73 Merge branch 'bugfix/spi2_add_device_cs_more_than_3_v4.3' into 'release/v4.3' 
spi_master:fix error when use `spi_bus_add_device` more than 3 device(v4.3)

See merge request espressif/esp-idf!20127
 2022-11-01 10:18:24 +08:00
Jiang Jiang Jian
6225c718c3 Merge branch 'bugfix/fix_xtal_related_rtc_params_for_esp32_backport_v4.3' into 'release/v4.3' 
esp32/rtc: fix xtal unstable in some cases when sleep(backport v4.3)

See merge request espressif/esp-idf!20804
 2022-10-31 19:52:04 +08:00
jingli
91b147c9da wifi/bt: fix part of modem module not reset when power up 2022-10-26 20:47:10 +08:00
jingli
b6491464e1 esp32/rtc: fix xtal unstable in some cases when sleep 
1. add xtal buf wait to fix high temperature restart issue
2. add min sleep value to fix xtal stop due to too short sleep time issue
 2022-10-26 17:05:07 +08:00
chenjianhua
0446de4429 Revert "component/bt: add local irk to controller" 
This reverts commit 032f6d34d1.
 2022-10-09 15:28:39 +08:00
jingli
07d69b7cae esp_hw_support/clk_cali: fix xtal32k error detect 2022-09-21 16:29:36 +08:00
wanlei
8290d450f3 spi_master:fix error when use spi_bus_add_device more than 3 device 
update gpio_sig at `spics_out` array in each spi_periph.c of chips later than s2
then `spi_bus_add_device` can correctly distribute gpio_signals for cs_signal

Closes https://github.com/espressif/esp-idf/issues/8876
 2022-09-14 12:40:29 +08:00
Song Ruo Jing
3ce98867a0 rtc_clk: Fix wrong RC_SLOW clock frequency value on ESP32C3 2022-09-02 21:06:24 +08:00
wangmengyang
a471f1e18e fix licence copyright for header file syscon_reg.h on ESP32C3 and ESP32S3 
# Conflicts:
#	components/soc/esp32s3/include/soc/syscon_reg.h
 2022-07-13 17:35:27 +08:00
wangmengyang
580b57c8b1 component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3 
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and MAC bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
 2022-07-13 17:35:22 +08:00
KonstantinKondrashov
0a71dce1ef reset_reasons: EFUSE_RST is treated as POWERON_RST 
ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
 2022-06-22 17:56:32 +08:00
KonstantinKondrashov
4e0e261f4e soc: Fix description of efuse fail bits 2022-06-09 10:35:25 +00:00
Jiang Jiang Jian
1b40e6173e Merge branch 'bugfix/i2c_timeout_issue_v4.3' into 'release/v4.3' 
I2C: patch for solving watchdog timeout issue(backport v4.3)

See merge request espressif/esp-idf!18132
 2022-06-09 11:10:57 +08:00
Wu Zheng Hui
a0b1d016e4 efuse: update efuse name (backport v4.3) 2022-05-31 14:42:05 +08:00
Cao Sen Miao
75f6279c22 I2C: patch for solving watchdog timeout issue 2022-05-17 16:56:58 +08:00
chaijie
908192f504 solve memory error bug when in lightsleep mode 2022-05-16 19:42:56 +08:00
Jiang Jiang Jian
1955dcda69 Merge branch 'bugfix/bootloader_uart_custom_gpio_v4.3' into 'release/v4.3' 
bootloader: fixed the issue custom_uart_gpio doesn't take effect (v4.3)

See merge request espressif/esp-idf!17308
 2022-03-03 16:49:49 +08:00
songruojing
5f3f615ff1 uart: fixed incorrect channel number on ESP32S2, S3 and C3 2022-03-02 02:56:23 +08:00
wuzhenghui
b8bd3ada55 remove esp32c3 unsupported efuse field 2022-02-28 18:58:12 +08:00
Michael (XIAO Xufeng)
6f99b8da73 Merge branch 'bugfix/gpio_pin_num_fix_v4.3' into 'release/v4.3' 
gpio: Fix some gpio pin num errors on esp32s2 and esp32c3 (backport v4.3)

See merge request espressif/esp-idf!17109
 2022-02-23 03:28:15 +00:00
Michael (XIAO Xufeng)
8ff2ce6852 soc: updated soc_caps about rtc_io and the format 2022-02-18 11:11:24 +08:00
songruojing
b1017de2e6 gpio: Fix some gpio pin num errors on esp32s2 and esp32c3 2022-02-10 20:27:43 +08:00
Cao Sen Miao
9c4b96d63b USB_SERIAL_JTAG: Fix the issue that there is no rom log when restarting 2022-02-10 10:33:40 +08:00
KonstantinKondrashov
5ebbe6aea7 efuse: Fixes eFuse timesettings issue on esp32c3 2022-01-25 19:16:16 +08:00
Jiang Jiang Jian
54b25318cd Merge branch 'bugfix/remove_dis_rtc_ram_boot_efuse_bit_backport_v4.3' into 'release/v4.3' 
efuse: remove DIS_RTC_RAM_BOOT efuse bit (backport v4.3)

See merge request espressif/esp-idf!15233
 2021-10-26 03:59:46 +00:00
Wu Zheng Hui
e5bd4427e3 fix efuse err address in block0 (backport v4.3) 2021-10-22 13:06:40 +08:00
wuzhenghui
fd5a63f31e modify csv & generate 
update efuse_reg.h & efuse_struct.h & references in rst file
 2021-10-21 19:24:12 +08:00
Cao Sen Miao
ce9e615679 Merge branch 'feature/esp32c3_usbjtagserial_v4.3' into 'release/v4.3' 
usb_serial_jtag: support usb_serial_jtag on esp32c3(backport v4.3)

See merge request espressif/esp-idf!15319
 2021-10-14 10:38:02 +00:00
suda-morris
91fa868bd6 twai: update register struct file 2021-10-12 10:42:04 +08:00
SalimTerryLi
29accf2533 soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one 
Note: on ESP32 UART rxfifo seems to be read as u8 instead of u32 to make it work
 2021-10-12 10:42:04 +08:00
Jeroen Domburg
d6cdb3e0ae usb_serial_jtag: support usb_serial_jtag on esp32c3 
USB serial/jtag controller: Add vfs (logging/printf), panic handler, gdb support.

See merge request espressif/esp-idf!12925
 2021-10-11 17:34:24 +08:00
Li Shuai
4f71b49aa6 esp_hw_support: keep external 40 MHz xtal related analog circuit power on during sleep 2021-09-28 11:21:33 +08:00
Li Shuai
aac59ed5ec Power Management: add XTAL power domain to control whether external 40MHz xtal is powered down during sleep 2021-09-28 11:21:31 +08:00
Li Shuai
4f4254537c esp_hw_support: No voltage drop during light sleep to ensure stable output clock of rtc8m oscillator 2021-09-28 11:20:00 +08:00
Li Shuai
4ef6e37fcb Power Management: add RTC8M power domain to control whether internal 8m oscillator is powered down during sleep 2021-09-28 11:19:57 +08:00
Sachin Parekh
c215bb04f6 hmac: Added Downstream JTAG enable mode for esp32c3 
If JTAG is disabled temporarily by burning SOFT_DIS_JTAG, it can be
re-enabled temporarily through esp_hmac_jtag_enable API
 2021-09-14 17:05:01 +05:30
xiewenxiang
032f6d34d1 component/bt: add local irk to controller 2021-08-06 18:19:25 +08:00
Wang Meng Yang
1537cff293 Merge branch 'bugfix/btdm_esp32_ble_white_list_connection_fail_v4.3' into 'release/v4.3' 
Fixed ESP32 BLE can't resolve the peer address when enable white list(release v4.3)

See merge request espressif/esp-idf!14558
 2021-07-30 23:58:22 +00:00
xiewenxiang
192aa18c31 Fixed ESP32 BLE can't resolve the peer address when enable white list 2021-07-30 15:09:00 +08:00
Wangjialin
427fe1bcde uart: fix esp32c3 uart output garbage value after resetting 2021-07-21 15:31:50 +08:00
Darian Leung
9b014138bf Update TWAI driver docs and registers for esp32c3 
This commit updates the documentation and register struct
of the TWAI driver for the ESP32-C3. Note that the register
fields for ESP32-S3 have also been updated.
 2021-06-23 19:26:16 +08:00
Jiang Jiang Jian
e6f96717ff Merge branch 'bugfix/remove_uart2_c3_v4.3' into 'release/v4.3' 
uart: remove misleading ld files and soc defs for UART2 (v4.3)

See merge request espressif/esp-idf!13394
 2021-05-13 04:11:32 +00:00
Jiang Jiang Jian
ed76cc4dd4 Merge branch 'feature/support_adjust_voltage_storingInEfuse_open_glitch_rst_v4.3' into 'release/v4.3' 
ESP32c3: auto adjust voltage dbias storing in efuse and open glitch reset for ECO3  (backport v4.3)

See merge request espressif/esp-idf!13388
 2021-05-13 04:08:56 +00:00
Marius Vikhammer
38aa99d63d soc: merge C3 caps into a single soc_caps.h 2021-05-11 15:20:54 +08:00
chaijie
6d2bdfc5f5 1. open glitch reset for c3 ECO3; 
2. set digital & rtc voltage to about 1.15v which storing in efuse.
 2021-05-08 17:38:24 +08:00
Michael (XIAO Xufeng)
2bffeb7265 uart: fix misleading files for UART2 
Includes: header files, ld files and clk.c

ESP32-C3 only have UART0 and UART1.
 2021-04-29 14:23:13 +08:00
Michael (XIAO Xufeng)
6c38cc736a Merge branch 'bugfix/twai_esp32_errata_workarounds_backport_v4.3' into 'release/v4.3' 
TWAI: Add FIFO overrun handling and ESP32 hardware errata workarounds  (backport v4.3)

See merge request espressif/esp-idf!12984
 2021-04-28 08:12:06 +00:00