Commit Graph

8 Commits

Author SHA1 Message Date
Wu Zheng Hui
b98622c624 efuse: update efuse name 2022-05-28 22:03:16 +08:00
KonstantinKondrashov
6d11c57b2a efuse: Adds ERR_RST_ENABLE efuse for C3 and S3
Closes https://github.com/espressif/esp-idf/issues/8357
2022-03-02 18:48:42 +08:00
Wu Zheng Hui
85651b4791 efuse: remove DIS_RTC_RAM_BOOT efuse bit 2021-09-18 14:58:43 +08:00
wuzhenghui
9c5d1c7fcf fix s3 efuse err address in block0 2021-09-16 20:08:59 +08:00
SalimTerryLi
874a720286
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
2021-08-30 13:50:58 +08:00
Cao Sen Miao
11672dc9e5 soc: update the csv headers for esp32s3 2021-06-16 18:04:18 +08:00
Marius Vikhammer
e2919eca8e soc: add soc headers from S3 fpga bringup branch 2021-03-17 18:47:51 +08:00
Renz Bagaporo
79887fdc6c soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00