Commit Graph

187 Commits

Author SHA1 Message Date
Ivan Grokhotkov
a6c721b24c esp32[s2,s3]: fix _flash_rodata_align value in the linker scripts
Regression from 4702feeee. The TLS segment is located inside
.flash.rodata, so we need to get the alignment of that section, not
.flash.rodata_noload.
2021-07-01 16:13:31 +02:00
Zhang Jun Hao
4702feeeeb esp_wifi: move unused wifi log to noload section to save binary size 2021-07-01 10:18:37 +08:00
Jan Brudný
325deed208 esp32: update copyright notice 2021-06-04 11:51:06 +02:00
Ivan Grokhotkov
0535195983 freertos: fix TLS run-time address calculation
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.

Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.

Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
2021-04-21 13:45:21 +02:00
Omar Chebib
dd849ffc26 build: (Custom) App version info is now on a dedicated section, independent of the rodata alignment
It is now possible to have any alignment restriction on rodata in the user
applicaiton. It will not affect the first section which must be aligned
on a 16-byte bound.

Closes https://github.com/espressif/esp-idf/issues/6719
2021-04-19 12:53:08 +08:00
Renz Bagaporo
bbc599493e esp32: move common fragment definitions 2021-03-31 19:17:33 +08:00
Marius Vikhammer
8ac74082f1 soc: add dummy bytes to ensure instr prefetch always valid
The CPU might prefetch instructions, which means it in some cases
will try to fetch instruction located after the last instruction in
flash.text.

Add dummy bytes to ensure fetching these wont result in an error,
 e.g. MMU exceptions
2021-03-29 13:50:03 +08:00
Renz Bagaporo
c6f0d47758 esp32: move bt linker script placements to ldgen 2021-03-01 14:19:34 +08:00
Renz Bagaporo
115b6ac0ac esp32: transfer coredump linker script blocks to ldgen 2021-03-01 14:19:34 +08:00
Renz Bagaporo
633ead5dcb esp32: move coredump sections and schemes to espcoredump 2021-03-01 14:19:34 +08:00
Renz Bagaporo
4bf07ae7d9 esp32: move wifi related sections and schemes to esp_wifi 2021-03-01 14:19:34 +08:00
Renz Bagaporo
b99777066f ldgen: implement flags support
Implement support for KEEP, ALIGN, emitting symbols and SORT.
Add appropriate tests
Defines default mapping in linker fragment file
2021-03-01 14:19:34 +08:00
ninh
659d805411 esp_wifi: light sleep optimization 2021-01-18 15:31:03 +08:00
Angus Gratton
db4fb49432 esp_common: Fix issue with SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY not visible on c3
Create a common symbol name to use from linker.lf fragments
2020-12-31 15:20:05 +11:00
xiehang
c41f4a122a esp_wifi: ESP32 phy add [sections:phy_iram] 2020-12-25 16:46:36 +08:00
Angus Gratton
55155c3f82 esp_system: Rename _init_start symbol to _vector_table 2020-12-24 13:40:01 +11:00
Sachin Parekh
be5563207d esp32: Provision to redirect .bss to external ram through linker fragments
Include external ram section in the linker template to process it
through linker script generation mechanism. This enables redirection of .bss section to external memory using linker fragments

libnet80211, libpp, libbt, liblwip: Redirect .bss through fragments
2020-12-04 06:32:38 +00:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Ivan Grokhotkov
ef10c2576f esp32: allow up to 8 kB of ULP program size
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.

Closes https://github.com/espressif/esp-idf/issues/3993
2020-10-05 11:41:39 +02:00
Darian Leung
97721d469c TWAI: Add ESP32-S2 support
This commit adds TWAI driver support for the
ESP32-S2. The following features were added:

- Expanded BRP support
- Expanded CLKOUT Divider Support
- Updated example READMEs
2020-06-30 16:56:03 +08:00
Renz Christian Bagaporo
0f43a2620d esp_system: component init functions macro
Allows components to declare initialization function, such that the
startup code does not have direct dependency on the component.
2020-06-19 18:40:09 +10:00
Alexey Gerenkov
1deeadf4c5 Added coredump user defined variable into coredump 2020-06-15 02:35:38 +08:00
Sachin Parekh
46d914ff45 gdb: Modify PC in case of invalid PC
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-05-08 18:34:52 +05:30
Mahavir Jain
44939a6b1e Merge branch 'feature/iram_data_bss' into 'master'
esp32: IRAM_DATA_ATTR and IRAM_BSS_ATTR introduced

See merge request espressif/esp-idf!8377
2020-04-22 21:44:44 +08:00
Sachin Parekh
1e6c25992e esp32: IRAM_DATA_ATTR and IRAM_BSS_ATTR introduced
Using these attributes, .data and .bss can be placed in IRAM

Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-04-17 19:35:23 +05:30
Jakob Hasse
4943b1cbf0 CXX: make __attribute__((init_priority(n))) work
* Added corresponding test case
* Moved all C++ init tests to separate file

Closes https://github.com/espressif/esp-idf/issues/5038
2020-04-08 09:11:54 +08:00
Ivan Grokhotkov
cbb84e8f5e esp32s2: fix THREADPTR calculation, re-enable FreeRTOS TLS tests
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.

2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.

Full explanation of the calculation below.

Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).

At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:

THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)

The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to

THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).

The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.

Closes IDF-1239
2020-01-23 11:29:22 +01:00
Renz Christian Bagaporo
df26ab13e2 test_utils: implement performance timer 2019-11-18 10:29:01 +08:00
xiehang
5e7f43f3d1 esp_wifi: Put some rx code to iram 2019-11-13 11:44:23 +00:00
Anton Maklakov
d86ec0f367 Revert "C++: add provisions for optional RTTI support"
This reverts commit 499d087c91.
2019-10-31 10:12:16 +07:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Ivan Grokhotkov
499d087c91 C++: add provisions for optional RTTI support
Ref. https://github.com/espressif/esp-idf/issues/1684

This change allows RTTI to be enabled in menuconfig. For full RTTI
support, libstdc++.a in the toolchain should be built without
-fno-rtti, as it is done now.

Generally if libstdc++.a is built with RTTI, applications which do not
use RTTI (and build with -fno-rtti) could still include typeinfo
structures referenced from STL classes’ vtables. This change works
around this, by moving all typeinfo structures from libstdc++.a into
a non-loadable section, placed into a non-existent memory region
starting at address 0. This can be done because when the application
is compiled with -fno-rtti, typeinfo structures are not used at run
time. This way, typeinfo structures do not contribute to the
application binary size.

If the application is build with RTTI support, typeinfo structures are
linked into the application .rodata section as usual.

Note that this commit does not actually enable RTTI support.
The respective Kconfig option is hidden, and will be made visible when
the toolchain is updated.
2019-10-13 14:46:44 +02:00
Ivan Grokhotkov
5830f529d8 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-02 19:01:39 +02:00
Roland Dobai
5a916ce126 Support ELF files loadable with gdb 2019-09-24 07:19:50 +00:00
Angus Gratton
438d513a95 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-16 16:18:48 +10:00
Michael (XIAO Xufeng)
df27a50866 app_update: re-enable elf-sha256 2019-09-11 18:29:11 +08:00
KonstantinKondrashov
c543aac91e bootloader: API for the fast wakeup and custom using RTC mem
Added "Reserve RTC FAST memory for custom purposes" option.
Added a boot counter.
2019-08-21 11:44:37 +00:00
Tim Nordell
43393cf4d1 bootloader: Support for skipping validation upon wake from deep sleep
This saves time when waking up from deep sleep, but potentially decreases
the security of the system.  If the application able to modify itself
(especially areas that are loaded into RAM) in flash while running
without crashing or is modifies the cached bits of information about
what was last booted from the bootloader, this could cause security
issues if the user does a "deep sleep reset" since the full validation
is skipped.

Signed-off-by: Tim Nordell <tim.nordell@nimbelink.com>
2019-08-21 11:44:37 +00:00
suda-morris
90c4827bd2 add esp_eth component 2019-06-26 10:19:23 +08:00
Hrishikesh Dhayagude
342f6a7829 Port NimBLE Host Stack on ESP-IDF 2019-06-25 09:03:58 +08:00
Gautier Seidel
542e544faa esp32: Allow fixed static RAM size and DRAM heap size
Merges https://github.com/espressif/esp-idf/pull/3222
2019-06-06 18:23:04 +10:00
Angus Gratton
22514c1dd9 cmake: For gcc8 use linker to find paths to libc, libm, libstdc++, etc
Removes the need to know/guess the paths to these libraries. Once we are gcc 8 only, we
can remove -nostdlib and no additional arguments are needed for system libraries.

The catch is: any time IDF overrides a symbol in the toolchain sysroot, we need
an undefined linker marker to make sure this symbol is seen by linker.
2019-05-28 12:54:37 +08:00
Roland Dobai
0ae53691ba Rename Kconfig options (components/esp32) 2019-05-21 09:09:01 +02:00
morris
f5b03c9ea3 misc adjustment of esp32 component 2019-04-03 19:57:46 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
2019-03-21 18:51:45 +08:00
Angus Gratton
a79c5b8271 esp32: Rename esp32.common.ld to esp32.project.ld to avoid build errors when downgrading
Linker script generator produces build/esp32/esp32.common.ld from
components/esp32/ld/esp32.common.ld.in

This works fine until IDF is downgraded to V3.1 which uses components/esp32/ld/esp32.common.ld and
doesn't track build/esp32/esp32.common.ld at all.

At this point, the linker runs in the build/esp32 directory and "-T esp32.common.ld" picks up the
linker script generated .ld file, which causes mis-builds.

As reported on forums: https://esp32.com/viewtopic.php?f=13&t=9684&p=40105
2019-03-14 09:59:31 +11:00
Liu Zhi Fu
711173b3d6 esp32: make WiFi IRAM optimization configurable
With this feature, the WiFi IRAM optimization can be disabled/enabled via menuconfig.
2019-02-26 19:55:57 +08:00
Angus Gratton
5b182eefc1 Merge branch 'bugfix/spiram_linker_wildcards' into 'master'
newlib: Provide library name for ROM libc object files linked as PSRAM workarounds

See merge request idf/esp-idf!4152
2019-02-19 13:28:10 +08:00
baohongde
27235e023f components/bt: Fix crash when inquiry stop 2019-01-31 11:47:41 +08:00
Angus Gratton
7f307423c1 newlib: Provide library name for ROM libc object files linked as PSRAM workarounds
Works around bug reported on forums where any source file ending in *lock.c or *creat.c
was being linked to IRAM.

https://esp32.com/viewtopic.php?f=13&t=8909&p=37362#p37362

Also moves all related functionality to newlib component.
2019-01-24 11:30:05 +08:00