esp32: Fixes watchdog problem when printing core dump to uart
1) Fixes watchdog problem when printing core dump to uart
2) Also fixes generation of core dumps when flash cache is disabled
See merge request !472
1. fix ampdu<->mpdu<->ampdu switch may cause rx slow issue by put mpdu into ampdu reorder queue
2. fix each ac first sending always fail issue by adding retry
1. modify the discover retry backoff time from (2,4,8,16,32,60,60)s to (500m,1,2,4,8,15,15)s.
2. add DHCP_DOES_ARP_CHECK to menuconfig for users to specify if do a ARP check on the offered address.
If enable, one more second will be taken in obtaining IP address.
3. update wifi libs
Move PHY options out of WiFi config, improve descriptions
- move PHY-related settings into new menu, make it dependent on WIFI_ENABLED || BT_ENABLED
- improve descriptions of Ethernet Kconfig options
See merge request !443
ESP32_PHY_MAX_TX_POWER option is only meaningful for WiFi, so previous
change made it depend on WIFI_ENABLED. However if WiFi is not enabled,
but BT is, this option becomes undefined which breaks phy_init_data
generation.
This change turns ESP32_PHY_MAX_TX_POWER into a hidden parameter, which
depends on PHY_ENABLED. New user-visible parameter,
ESP32_PHY_MAX_WIFI_TX_POWER is introduced which depends on WIFI_ENABLED
and is used as default value for ESP32_PHY_MAX_TX_POWER if WIFI_ENABLED
is set. Otherwise ESP32_PHY_MAX_WIFI_TX_POWER is set to 20.
fixes for issues observed when using spi_flash
This MR fixes three unrelated issues:
- Race condition in spi_flash_enable_interrupts_caches_and_other_cpu
when operations on unpinned tasks are performed.
The issue is reported in https://github.com/espressif/esp-idf/pull/258
- esp_intr_noniram_disable doesn’t disable interrupts when compiled in
release mode. This issue manifested itself with an illegal instruction
exception when task WDT ISR was called at the time when flash was
disabled.
Fixes https://github.com/espressif/esp-idf/issues/263.
- Tick hooks on CPU1 were not called if CPU0 scheduler was disabled for
significant amount of time (which could happen when doing flash erase).
The issue manifested itself as “INT WDT timeout on core 1” error.
Fixes https://github.com/espressif/esp-idf/issues/219.
See merge request !441
When compiling in release mode, compiler was choosing same register for
oldint and intmask variables, so INTENABLE was never modified.
This effectively broke disabling of non-IRAM interrupts during flash
operations, observed in the existing tests if task watchdog is enabled.
This change adds an extra constraint tells the compiler that output
operand should not be placed into the same register as an input one.
Delete option to select core timer 2 as a FreeRTOS tick source
Core timer 2 is unusable for FreeRTOS ticks because it triggers a high-level interrupt. This MR deletes the option to select it.
Ref https://github.com/espressif/esp-idf/issues/234
See merge request !418
update wifi lib: fix some wifi lib bugs
1. net80211: fix get ap info error(a4614877)
2. tw9358: sta mac same with softap(ea38d32c)
3. tw9221: scan channel error when connected(183d469c)
See merge request !425
fixes for github issues
This MR includes commits from several Github PRs, as well some fixes for issues reported on Github and on the forum.
- compile PHY-related code only when WiFi is enabled
- fix macOS setup instructions
- fix some of the Sphinx warnings
- update docs index, improve structure of the readme-
- wifi: fix typos, rename ESP_ERR_WIFI_NOT_START to ESP_ERR_WIFI_NOT_STARTED
- sdmmc: fix explanation of flash voltage regulator configuration efuses
- sdmmc: change idx num of example
- fix i2c_get_period name
- fix esp_log_level_set function name in docs
See merge request !420
If using WIFI_INIT_CONFIG_DEFAULT, error message will point out lack
of WiFi. Otherwise linker errors on WiFi symbols should help give a
clue as to what is broken.
Piggy-backs on changes in !420, ref github #230#237
esp32 core dump to flash
1. menuconfig option to select where to store core dump: flash, uart or disable
2. Saving of core dump to flash
3. Partition table definitions files with core dump partition
4. Python scripts to support core dump generation from GDB command line
See merge request !341
The following issues mentioned during MR!341 review were fixed:
1) Core dump test application description
2) Usage of CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH and CONFIG_ESP32_ENABLE_COREDUMP_TO_UART
3) FLASH_GUARD_START macro usage is fixed in flash API
4) Core dump module logging facility
5) cache util functions doc updated
6) interactive delay before print core dump to uart
7) core dump partion support in build system
Deep sleep stub may call ets_update_cpu_frequency, which has been moved from ROM to IRAM.
Restore the ROM version in the linker script, call it ets_update_cpu_frequency_rom, use it in the deep sleep stub.
1) PS is fixed up to allow GDB backtrace to work properly
2) MR!341 discussion: in core dump module: esp_panicPutXXX was replaced by ets_printf.
3) MR!341 discussion: core dump flash magic number was changed.
4) MR!341 discussion: SPI flash access API was redesigned to allow flexible critical section management.
5) test app for core dump feature was added
6) fixed base64 file reading issues on Windows platform
7) now raw bin core file is deleted upon core loader failure by epscoredump.py
Complimentary changes:
1) Partition table definitions files with core dump partition
2) Special sub-type for core dump partition
3) Special version of spi_flash_xxx
4) espcoredump.py is script to get core dump from flash and print useful info
5) FreeRTOS API was extended to get tasks snapshots
Clean up WiFi & Bluetooth config options
* Splits "WiFi" configuration out from ESP32 configuration submenu to its own menu.
* Renames "BT" to "Bluetooth", enabling Bluetooth is now in this option not the ESP32 submenu.
* Also disables compiling/linking of BT stack if Bluetooth is disabled, saves some build time.
See merge request !397
add wpa2 set id api and modify null data tx description
1. wpa2: add wpa2 set id api
2. low rate: modify null data tx description
See merge request !402
ethernet: support flow control
(1) Only fullduplex mode support flow ctrl .
(2) Fix reboot exception which caused by not-reset EMAC hardware (such as DMA) when reset CPU.
See merge request !392
Add option to automatically set a watchpoint at the end of the swapped-in task
This should make stack overflows easier to debug because it triggers a debug exception as soon as the stack is overwritten, not later when a context switch happens. Marked as a FreeRTOS debug feature because it doesn't give a nice error message and uses up a watchpoint.
See merge request !389
Fix OpenOCD detection code
In the current master, detection of an attached OCD is broken. This fixes it.
I also snuck in two unrelated checks in intr_alloc which return from a function that is asserted earlier in the code. This makes the code behave better when they are called erroneously in a production build.
See merge request !377
SDMMC peripheral driver, SD protocol driver, FATFS library, VFS integration
This MR contains:
- SDMMC host peripheral driver
- SD protocol driver in sdmmc component (can be extended to support MMC/eMMC and SPI based hosts)
- ChaN's FATFS library v0.12b
- VFS integration
- FAT access via VFS is thread-safe (unless same file is read/written/unlinked/renamed from different tasks)
- Support for POSIX directory-related functions in VFS (and in vfs_fatfs.c)
- unit test for the above
- Example
- API documentation
Will be done in other MRs:
- Support for spi_flash IO driver for FatFs
- SPI host driver and support for SPI mode commands in sdmmc component
- MMC/eMMC support in sdmmc component
- Support for slightly higher 53/26.6MHz clocks (currently I'm using 20MHz for DS and 40MHz for HS, instead of 25MHz/50MHz per standard), and arbitrary low clocks (e.g. 4MHz).
See merge request !353
C++ support
This change adds necessary support for compiling C++ programs:
- linking against libstdc++
- implementation of static initialization guards using FreeRTOS primitives: since we don't have condition variables at our disposal, and we don't want to allocate a synchronization primitive for every guard variable generated by the compiler, we imitate condition variables using a combination of a mutex, counting semaphore, and a counter (based on [Microsoft Research paper](https://www.microsoft.com/en-us/research/wp-content/uploads/2004/12/ImplementingCVs.pdf), albeit because we don't need *arbitrary* code to use these CVs, implementation gets simpler).
Note that libstdc++ also contains an implementation of `__cxa_guard_{acquire,release,abort}` functions. These implementations come from an `#ifndef GXX_THREADS` branch, i.e. are not aware of multthreading. There are three ways of replacing these libstdc++ functions with our implementation:
1. Move our code into gcc. Pros: cleanest solution. Cons: Such changes are unlikely to be merged by any upstream, so we end up maintaining our own forks of {gcc,crosstool-ng}.
2. Use library as it is built by crosstool, use `ar` to delete one object file (`guards.o`), add this library to ESP-IDF. Pros: easy to implement. Cons: libstdc++ is a 15MB binary 😯
3. Keep using libstdc++ from crosstool, force our implementation to be linked using a `-u` linker flag. Pros: no impact on repo size, easy to implement. Cons: somewhat less clean than 1 (and about as hacky as 2).
For the reasons mentioned, option (3) looks like the best tradeoff.
Ref. TW6702
See merge request !364
Enable bootloader entropy source for RNG
Enables an entropy source when bootloader starts up, which both seeds the RNG for use before WiFi/BT stack is enabled and provides an adequate RNG for secure boot & flash encryption key generation.
A prerequisite was enabling 80MHz operation, so the CPU is now set to 80MHz as soon as second stage bootloader starts running.
See merge request !363
esp32: ets_update_cpu_frequency should set tick scale for both CPUs
ets_update_cpu_frequency ROM function updates g_ticks_per_us, which is has two copies, one for each CPU.
The APP CPU copy of g_ticks_per_us never got updated, resulting in shorter delays produced by ets_delay_us on the APP CPU.
This MR replaces ROM ets_update_cpu_frequency with a copy in IRAM which updates scaling factors on both of the CPUs.
So now we get expected delays (in microseconds):
```
ets_delay_us core=0 expected=50000 actual=50014
ets_delay_us core=1 expected=50000 actual=50015
vTaskDelay core=0 expected=50000 actual=49428
vTaskDelay core=1 expected=50000 actual=50000
```
Reported on the forum: http://esp32.com/viewtopic.php?f=2&t=713#p3722
See merge request !373
SPI master driver
This merge requests adds an SPI Master driver. This driver is (of course) multithread capable, has device abstraction, has command queueing, DMA support and all other sorts of nice things you'd expect from a SPI driver.
See merge request !332
modify bootloader dram start address, swap app bss and data segments
Modify bootloader dram_seg from address 0x3ffc0000 to 0x3fff0000, len from 0x20000 to 0x10000.
Also put app .data before .bss, to reduce the chance .data collides with ROM bootloader stack.
See merge request !375
This change reduces chances that a large .bss segment will push .data all the way into
0x3ffe1320 — 0x3ffe5320 range where the bootloader stack is, creating a problem when
bootloader will be loading application into memory.
With this change, .data would need to be at least 200k big to cause problems.
1. Update wifi lib which contains ampdu and other optimizations
2. Add throughput code debug code
3. Other misc modification about throughput optimization
2. update example comments and other minor changes
3. rename API: i2c_cmd_link_create/i2c_cmd_link_delete (+4 squashed commits)
Squashed commits:
[2e0ac3e] 1. coding style: add one space after condition key words.
2. modify i2c.h, use gpio_num_t instead of int, improve comments of return values
3. add i2c index in index.rst
4. add readme for i2c example
[4991d92] update i2c.doc
[88b672e] driver: i2c
1. add mux and spin lock to run in a thread-safe way.
2. modify example code
[4eb15fe] driver: i2c code
1. add i2c master code
2. add i2c slave code
3. add i2c example code
4. add DRAM_ATTR for I2C array
