On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.
Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.
This commit marks all functions in soc_hal.h and soc_ll.h as deprecated.
Users should use functions from esp_cpu.h instead.
Also added missing wrap funcions for esp_cpu_stall() in test_panic.c files.
