Commit Graph

16 Commits

Author SHA1 Message Date
Ivan Grokhotkov
cf5ef7f0e1 freertos: don't clobber a4 while spilling register windows
Commit 891eb3b0 was fixing an issue with PS and EPC1 not being
preserved after the window spill procedure. It did so by saving PS in
a2 and EPC1 in a4. However the a4 register may be a live register of
another window in the call stack, and if it is overwritten and then
spilled to the stack, then the corresponding register value will end
up being corrupted. In practice the problem would show up as an
IllegalInstruction exception, when trying to return from a function
when a0 value was 0x40020.
Fix by using a0 register instead of a4 as scratch. Also fix a comment
about xthal_save_extra_nw, as this function in fact doesn't clobber
a4 or a5 because XCHAL_NCP_NUM_ATMPS is defined as 1.

Closes https://github.com/espressif/esp-idf/issues/5758
2020-11-11 14:43:15 +00:00
Ivan Grokhotkov
891eb3b020 freertos: save/restore PS and EPC1 around window spilling
Since in b0491307, which has introduced the optimized window spill
procedure, _xt_context_save did not work correctly when called from
_xt_syscall_exc. This was because unlike _xt_lowint1, _xt_syscall_exc
does not save PS and EPC1. The new version of _xt_context_save
modified PS (on purpose) and EPC1 (accidentally, due to window
overflow exceptions), which resulted in a crash upon 'rfi' from the
syscall.

This commit adds restoring of PS and EPC1 in _xt_context_save. It also
slightly reduces the number of instructions used to prepare PS for
window spill.

Unit test for setjmp/longjmp (which were broken by this regression)
is added.

Closes https://github.com/espressif/esp-idf/issues/4541
2019-12-27 11:27:01 +01:00
KonstantinKondrashov
1687c53700 freertos: Fix save_context. Add RSYNC after WSR
RSYNC waits for all previously fetched WSR.* instructions to be performed before inter-
preting the register fields of the next instruction.
2019-12-21 14:10:38 +00:00
Felipe Neves
64a50f0423 components/freertos: fixed isr test failling when run multiple times 2019-12-04 10:40:27 -03:00
Felipe Neves
bcdc35be59 components/freertos: refactor of isr_latency tests to perform full measurement 2019-12-04 10:39:22 -03:00
Felipe Neves
8b6b97ec57 freertos/xtensa_context: fixed small typo 2019-12-04 10:39:22 -03:00
Felipe Neves
c14fc39b0a components/freertos: fixed typos and licence placement on external code 2019-12-04 10:39:22 -03:00
Felipe Neves
64f918bd70 freertos/xtensa_context: added conditional compiling option around isr cycle measurement
It is possible to enable and disable the isr time measurement on context save and
it related test via menuconfig by the new option: FREERTOS_ISR_STATS
2019-12-04 10:39:22 -03:00
Felipe Neves
346b12e29a freertos/test: added spill register timer measurement test 2019-12-04 10:39:22 -03:00
Felipe Neves
5ce7a33c87 freertos/xtensa_context.S: fix some dread tabs 2019-12-04 10:39:22 -03:00
Felipe Neves
cd11787153 freertos/xt_asm_utils: added documentation of current windows spill solution 2019-12-04 10:39:22 -03:00
Felipe Neves
768d115e85 freertos/Kconfig: removed isr optimization option from menuconfig 2019-12-04 10:39:22 -03:00
Felipe Neves
eb740ca8e4 freertos/xtensa_context: modification of interrupt handler is workin, needs stabilization 2019-12-04 10:39:22 -03:00
Felipe Neves
d185625162 freertos/xtensa_context: added infrastructure to receive the spill register optimized code 2019-12-04 10:39:22 -03:00
jack
fc130fba86 fix bug that files missing commit in MR 773 2017-05-31 19:37:39 +08:00
Ivan Grokhotkov
bd6ea4393c Initial public version 2016-08-17 23:08:22 +08:00