cpu retention: add riscv core sleep critical and non-critical register layout structure definition
cpu retention: add assembly subroutine for cpu critical register backup and restore
cpu retention: add cpu core critical register context backup and restore support
cpu retention: add cpu core non-critical register context backup and restore support
cpu retention: add interrupt priority register context backup and restore support
cpu retention: add cache config register context backup and restore support
cpu retention: add plic interrupt register context backup and restore support
cpu retention: add clint interrupt register context backup and restore support
cpu retention: wait icache state idle before pmu enter sleep
- Move {target}/rom/miniz.h to common miniz.h
- Add ESP_ROM_HAS_MZ_CRC32 for ESP32/S2/S3/C3/H4
- Alias mz_crc32 to crc32_le if chips not support ESP_ROM_HAS_MZ_CRC32
Closes https://github.com/espressif/esp-idf/issues/10177