introduced in e44ead5356
1. The int8M power domain config by default is PD. While LEDC is using
RTC8M as clock source, this power domain will be kept on.
But when 8MD256 is used as RTC clock source, the power domain should
also be kept on.
On ESP32, there was protection for it, but broken by commit
e44ead5356. Currently the power domain
will be forced on when LEDC is using RTC8M as clock source &&
!int8m_pd_en (user enable ESP_PDP_DOMAIN_RTC8M in lightsleep). Otherwise
the power domain will be powered off, regardless of RTC clock source.
In other words, int8M domain will be forced off (even when 8MD256
used as RTC clock source) if LEDC not using RTC8M as clock source, user
doesn't enable ESP_PDP_DOMAIN_RTC8M, or in deep sleep.
On later chips, there's no such protection, so 8MD256 could't be used as
RTC clock source in sleep modes.
This commit adds protection of 8MD256 clock to other chips. Fixes the
incorrect protection logic overriding on ESP32. Now the power domain
will be determiend by the logic below (order by priority):
1. When RTC clock source uses 8MD256, power up
2. When LEDC uses RTC8M clock source, power up
3. In deepsleep, power down
4. Otherwise determined by user config of ESP_PDP_DOMAIN_RTC8M,
power down by default. (This is preferred to have highest
priority, but it's kept as is because of current code structure.)
2. Before, after the macro `RTC_SLEEP_CONFIG_DEFAULT` decides dbias, the
protection above may force the int8m PU. This may cause the inconsistent
of dbias and the int8m PU status.
This commit lifts the logic of pd int8m/xtal fpu logic to upper layer
(sleep_modes.c).
Related: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089
temp
When not compiling bootloader, a spinlock will be used for reading or writing
I2C internal devices/registers.
When compiling for bootloader, no need to use any lock.
1. deepsleep poweron reset bug in high temperature before ECO3;
2. brownout reset bug before ECO2;
3. bbpll voltage low bug before ECO3;
4. need xpd iph for xtal before ECO3;
1. Fix the bug that Wi-Fi performance is impacted by BLE starting scan for a while in some scenarios on ESP32-C3.
2. Fix the bug that Wi-Fi performance is impacted when Bluetooth change state for a while in some scenarios on ESP32-C3.
3. Fix the bug that BLE performance is impacted by Wi-Fi scan on ESP32-C3.
4. Fix the bug that Wi-Fi scan fails when BLE is scanning on ESP32-C3.
5. Fix Wi-Fi ACK and CTS rate when low rate is disabled on ESP32-C3.
Also:
1. Separate static configuration into init phase to improve
performance
2. Add a init code config layer to avoid duplicated configuration
3. Add a HW_CALIBRATION_V1 caps
esp32s2: fix wrong deepsleep configuration issue.
1. if RTC_CK8M_ENABLE_WAIT_DEFAULT set to 1, rtc peripherals will not poweron successfully if pd peripherals in light_sleep, the minimum RTC_CK8M_ENABLE_WAIT_DEFAULT is RTC_POWERUP_CYCLES + RTC_WAIT_CYCLES + 2;
2. when goto deepsleep after lightsleep waking up, rtc regulator should not force pu.
