Sudeep Mohanty
2ed15d8b1e
ulp: Added ULP RISC-V support for esp32s3
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This commit adds support for ULP RISC-V for esp32s3.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2022-01-18 10:58:00 +05:30
Angus Gratton
66fb5a29bb
Whitespace: Automated whitespace fixes (large commit)
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Apply the pre-commit hook whitespace fixes to all files in the repo.
(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Dmitry Yakovlev
0a8afd13a2
Udate instruction set documentation for Esp32 and Esp32s2.
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Sleep instruction removed from S2 instruction set.
LDx/STx instructions descritioin fix offset range to 13 bits (11 bits signed 32 bit words offset).
Remove I2C RD/WR operations from S2.
2020-10-17 02:44:47 +08:00
morris
e30cd361a8
global: rename esp32s2beta to esp32s2
2020-01-22 12:14:38 +08:00
Angus Gratton
6b7da96d5b
ulp: Add header for common ULP definitions
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Fixes problems with duplicate error codes in the two chip-specific ulp headers
2019-09-16 16:18:53 +10:00
